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    Semiconductor packages
    1.
    发明授权
    Semiconductor packages 有权

    公开(公告)号：US11476220B2

    公开(公告)日：2022-10-18

    申请号：US17146550

    申请日：2021-01-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jimin Choi ,  Jung-Hoon Han ,  Yeonjin Lee ,  Jong-Min Lee ,  Jihoon Chang

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L21/66

    Abstract: Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.

    Capacitor structures, decoupling structures and semiconductor devices including the same
    2.
    发明授权
    Capacitor structures, decoupling structures and semiconductor devices including the same 有权

    公开(公告)号：US10211282B2

    公开(公告)日：2019-02-19

    申请号：US15712365

    申请日：2017-09-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong-Min Lee ,  Jongryul Jun ,  Eun A Kim ,  Jung-Bum Lim

    IPC: H01L27/108 ,  H01L49/02 ,  H01L27/08

    Abstract: Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

    Method of forming fine patterns
    3.
    发明授权
    Method of forming fine patterns 有权

    公开(公告)号：US10050129B2

    公开(公告)日：2018-08-14

    申请号：US15437563

    申请日：2017-02-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Bum Lim ,  Jong-Ryul Jun ,  Eun-A Kim ,  Jong-Min Lee

    IPC: H01L21/336 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L21/027

    Abstract: A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.

    Capacitor structure and semiconductor device including the same
    4.
    发明授权
    Capacitor structure and semiconductor device including the same 有权

    公开(公告)号：US11594595B2

    公开(公告)日：2023-02-28

    申请号：US17156773

    申请日：2021-01-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Min Lee ,  Hyongsoo Kim ,  Jongryul Jun

    IPC: H01L27/108 ,  H01L49/02

    Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

    Capacitor structure and semiconductor device including the same
    6.
    发明授权
    Capacitor structure and semiconductor device including the same 有权

    公开(公告)号：US10903310B2

    公开(公告)日：2021-01-26

    申请号：US16787426

    申请日：2020-02-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Min Lee ,  Hyongsoo Kim ,  Jongryul Jun

    IPC: H01L49/02 ,  H01L27/108

    Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

    Semiconductor memory devices and methods of fabricating the same
    10.
    发明授权
    Semiconductor memory devices and methods of fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09379123B2

    公开(公告)日：2016-06-28

    申请号：US14848423

    申请日：2015-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

    IPC: H01L21/764 ,  H01L27/115 ,  H01L29/423

    CPC classification number: H01L27/11524 ,  H01L21/764 ,  H01L29/42324

    Abstract: Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

    Abstract translation: 提供一种半导体存储器件及其制造方法。 半导体存储器件可以包括半导体衬底，其具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，设置在第一区域上的栅电极以跨越有源区域， 存储图案，设置在所述栅电极和所述有源区之间，阻挡绝缘层，设置在所述栅电极和所述电荷存储图案之间并在所述第一沟槽上延伸以限定所述第一沟槽中的第一气隙，以及间隔开的绝缘图案 从第二沟槽的底表面到第二沟槽中限定第二气隙。

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