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    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20230043936A1

    公开(公告)日：2023-02-09

    申请号：US17735292

    申请日：2022-05-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae Jin PARK ,  Gyul GO ,  Jun Soo KIM ,  Gyung Hyun YOON ,  Eui Jun CHA ,  Hui-Jung KIM ,  Yoo Sang HWANG

    IPC: H01L27/108

    Abstract: A semiconductor device and a method for fabricating the same is provided. The semiconductor device includes a lower semiconductor film, a buried insulating film, and an upper semiconductor film which are sequentially stacked; an element isolation film defining an active region inside the substrate and including a material having an etching selectivity with respect to silicon oxide; a first gate trench inside the upper semiconductor film; a first gate electrode filing a part of the first gate trench; a second gate trench inside the element isolation film; and a second gate electrode filling a part of the second gate trench, a bottom side of the element isolation film being inside the lower semiconductor film.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20250079305A1

    公开(公告)日：2025-03-06

    申请号：US18648097

    申请日：2024-04-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun Soo KIM ,  Sung Ho JANG

    IPC: H01L23/528 ,  H10B41/30 ,  H10B43/30

    Abstract: A capacitor-less semiconductor memory device and a method for fabricating the same are provided. The semiconductor memory device includes a first metal-oxide semiconductor film, a second metal-oxide semiconductor film spaced apart from the first metal-oxide semiconductor film, a first gate electrode intersecting the first metal-oxide semiconductor film and the second metal-oxide semiconductor film, a first gate dielectric film interposed between the first metal-oxide semiconductor film and the first gate electrode, a charge storage film in the first gate dielectric film, the charge storage film extending along at least a portion of the first metal-oxide semiconductor film and connected to the second metal-oxide semiconductor film, a second gate electrode spaced apart from the first gate electrode and intersecting the second metal-oxide semiconductor film, and a second gate dielectric film interposed between the second metal-oxide semiconductor film and the second gate electrode.

    SEMICONDUCTOR DEVICE
    5.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240339540A1

    公开(公告)日：2024-10-10

    申请号：US18386898

    申请日：2023-11-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Beom Jin KIM ,  Guk Hee KIM ,  Young Woo KIM ,  Jun Soo KIM ,  Sang Cheol NA ,  Kyoung Woo LEE ,  Anthony Dongick LEE ,  Min Seung LEE ,  Myeong Gyoon CHAE ,  Seung Seok HA

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L29/7855 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first horizontal direction on an upper surface of the substrate, a field insulating layer surrounding a sidewall of the active pattern on the upper surface of the substrate, a first gate electrode extending in a second horizontal direction intersecting the first horizontal direction on the active pattern, a source/drain region disposed on at least one side of the first gate electrode on the active pattern, an upper interlayer insulating layer covering the source/drain region on the field insulating layer, a through via penetrating through the substrate, the field insulating layer and the upper interlayer insulating layer in a vertical direction, the through via spaced apart from the source/drain region in the second horizontal direction, a source/drain contact disposed inside the upper interlayer insulating layer on at least one side of the first gate electrode, the source/drain contact connected to the source/drain region, and a connection portion disposed inside the upper interlayer insulating layer, the connection portion connected to each of the through via and the source/drain contact, wherein a width of the connection portion in the first horizontal direction is greater than a width of the source/drain contact in the first horizontal direction.

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