公开(公告)号：US20240170340A1

公开(公告)日：2024-05-23

申请号：US18425390

申请日：2024-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun KIM

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

公开(公告)号：US20220085006A1

公开(公告)日：2022-03-17

申请号：US17313212

申请日：2021-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun KIM

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/423

Abstract: Disclosed is a semiconductor device comprising a substrate including a peripheral region and a logic cell region, a first channel pattern including a first and a second semiconductor pattern stacked vertically on the peripheral region, a first gate electrode across the first channel pattern and extending in a first direction, a second channel pattern including a third and a fourth semiconductor pattern stacked vertically on the logic cell region, and a second gate electrode across the second channel pattern and extending in the first direction, the second gate electrode having a second width in a second direction less than a first width in the second direction of the first gate electrode. The first gate electrode has a first thickness between the first and the second semiconductor pattern, and the second gate electrode has a second thickness between the third and the fourth semiconductor pattern greater than the first thickness.

公开(公告)号：US20250159970A1

公开(公告)日：2025-05-15

申请号：US19022063

申请日：2025-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun KIM

IPC: H10D84/03 ,  H01L21/28 ,  H10D64/01 ,  H10D64/66 ,  H10D64/68 ,  H10D84/01 ,  H10D84/83 ,  H10D84/85 ,  H10D86/00 ,  H10D86/01

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

公开(公告)号：US20220344329A1

公开(公告)日：2022-10-27

申请号：US17497449

申请日：2021-10-08

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Myungsoo SEO ,  Sangjung KANG ,  Juyoun KIM ,  Seulgi YUN ,  Seki HONG

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234

Abstract: A method of manufacturing a semiconductor device includes forming a dummy gate structure on a substrate, partially removing the dummy gate structure to form a first opening that divides the dummy gate structure, forming a first division pattern structure in the first opening, replacing the dummy gate structure with a gate structure, removing the first division pattern structure to form a second opening, removing a portion of the gate structure from a sidewall of the second opening to enlarge the second opening, and forming a second division pattern in the enlarged second opening.

公开(公告)号：US20210287947A1

公开(公告)日：2021-09-16

申请号：US17335174

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun KIM

IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/088 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L27/092 ,  H01L21/84 ,  H01L27/12

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

公开(公告)号：US20240096980A1

公开(公告)日：2024-03-21

申请号：US18368725

申请日：2023-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inyeal LEE ,  Deokhan BAE ,  Juyoun KIM

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate with first and second regions; first and second source/drain regions on the first and second regions; first and second source/drain contacts on the first and second source/drain regions; and a separation structure intersecting the active pattern between the first and second source/drain contacts, and extending into the active pattern between the first and second source/drain regions, wherein an upper surface of the second source/drain contact is higher than an upper surface of the first source/drain contact, and wherein the separation structure has an asymmetrical structure having an upper surface of a first portion adjacent to the first source/drain contact higher than an upper surface of a second portion adjacent to the second source/drain contact.

公开(公告)号：US20210408254A1

公开(公告)日：2021-12-30

申请号：US16950104

申请日：2020-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun KIM ,  Jinwoo KIM ,  Kyuman HWANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes first and second active regions on a substrate, an element isolation layer between the first and second active regions, a dummy gate line, dummy gate spacers at opposite side walls of the dummy gate line, and a dummy gate capping layer on the dummy gate line and. An upper surface of the element isolation layer is proximate to an upper surface of the substrate in relation to an upper end of the first active region in a vertical direction. The dummy gate line includes a horizontal section extending on the first active region to the element isolation layer in a horizontal direction, and a vertical section extending downwards from the horizontal section along a side wall of the first active region, the dummy gate line having an L shape, a vertical thickness of the horizontal section being smaller than a vertical thickness of the vertical section.

公开(公告)号：US20190189613A1

公开(公告)日：2019-06-20

申请号：US16174702

申请日：2018-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taewon HA ,  Juyoun KIM ,  Sang Min LEE ,  Moon-Sun HONG ,  Seki HONG

IPC: H01L27/088 ,  H01L21/28 ,  H01L29/51 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/28158 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/41791 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having an active region, and first to third transistors on the active region of the substrate, each of the first to third transistors including a dielectric layer on the substrate, a metal layer on the dielectric layer, a barrier layer between the dielectric layer and the metal layer, and a work function layer between the dielectric layer and the barrier layer, wherein the barrier layer of the third transistor is in contact with the dielectric layer of the third transistor, and wherein a threshold voltage of the second transistor is greater than a threshold voltage of the first transistor and less than a threshold voltage of the third transistor.

公开(公告)号：US20230029263A1

公开(公告)日：2023-01-26

申请号：US17958805

申请日：2022-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun KIM

IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/088 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L27/092 ,  H01L21/84 ,  H01L27/12

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

公开(公告)号：US20200335403A1

公开(公告)日：2020-10-22

申请号：US16921037

申请日：2020-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun KIM

IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/088 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L27/092 ,  H01L21/84 ,  H01L27/12

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.