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    METHOD OF OPERATING MEMORY DEVICE AND METHODS OF WRITING AND READING DATA IN MEMORY DEVICE
    1.
    发明申请
    METHOD OF OPERATING MEMORY DEVICE AND METHODS OF WRITING AND READING DATA IN MEMORY DEVICE 有权
    操作存储器件的方法和在存储器件中写入和读取数据的方法

    公开(公告)号：US20150067448A1

    公开(公告)日：2015-03-05

    申请号：US14305095

    申请日：2014-06-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong-Pil SON ,  Young-Soo SOHN ,  Uk-Song KANG ,  Chul-Woo PARK ,  Jung-Hwan CHOI ,  Won-Il BAE ,  Kyo-Min SOHN

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0411

    Abstract: In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.

    Abstract translation: 在操作存储器件的方法中，接收来自存储器控制器的命令和第一地址。 从存储器件的存储单元阵列读取包括对应于第一地址的第一组数据，对应于第二地址的第二组数据和读取奇偶校验数据的读码字。 通过使用基于读取的线字的ECC电路的操作错误检查和校正（ECC）来生成校正的数据。

    DEVICE AND SYSTEM INCLUDING ADAPTIVE REPAIR CIRCUIT
    4.
    发明申请
    DEVICE AND SYSTEM INCLUDING ADAPTIVE REPAIR CIRCUIT 有权
    包括自适应维修电路的设备和系统

    公开(公告)号：US20150363258A1

    公开(公告)日：2015-12-17

    申请号：US14739534

    申请日：2015-06-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Hoon SHIN ,  Hae-Suk LEE ,  Han-Vit JUNG ,  Kyo-Min SOHN

    IPC: G06F11/07

    CPC classification number: G06F11/0793 ,  G06F11/0703 ,  G06F11/0796 ,  G06F11/142 ,  G06F11/1423 ,  G06F11/1616 ,  G06F11/18 ,  G06F11/2002 ,  G06F11/2017

    Abstract: A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.

    Abstract translation: 一种设备，系统和/或方法包括被配置为执行至少一个功能的内部电路，输入 - 输出端子组和修复电路。 输入输出端子组包括经由多个正常信号路径连接到外部设备的多个正常输入 - 输出端子和经由至少一个修复信号路径有选择地连接到外部设备的至少一个修复输入 - 输出端子。 修复电路基于模式信号和故障信息信号修复包括在正常信号路径中的至少一个故障信号路径，其中模式信号表示是否使用修复信号路径，并且故障信息信号表示正常信号的故障信息 路径。 使用维修电路，可以修复采用不同维修方案的各种系统，并且可以降低各种系统的设计和制造成本。

    REPAIR CIRCUIT AND FUSE CIRCUIT
    6.
    发明申请
    REPAIR CIRCUIT AND FUSE CIRCUIT 有权
    维修电路和保险丝电路

    公开(公告)号：US20150325316A1

    公开(公告)日：2015-11-12

    申请号：US14595500

    申请日：2015-01-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyu-Chang KANG ,  Gil-Su KIM ,  Je-Min RYU ,  Yun-Young LEE ,  Kyo-Min SOHN

    IPC: G11C29/00 ,  G11C17/18 ,  G11C17/16

    CPC classification number: G11C29/76 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/78 ,  G11C2029/4402

    Abstract: A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.

    Abstract translation: 修复电路包括第一和第二熔丝电路，确定电路和输出电路。 第一熔丝电路包括第一熔丝，并且被配置为产生指示第一熔丝是否已被编程的第一主信号。 第二熔丝电路包括第二保险丝，并且被配置为产生指示每个第二保险丝是否被编程的第一地址。 确定电路被配置为基于第一主信号和第一地址产生检测信号。 检测信号指示是否对第二熔丝电路执行了负编程操作。 输出电路被配置为基于第一主信号和检测信号产生第二主信号，并且基于第一地址和检测信号产生对应于有缺陷的输入地址的修复地址。

    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200151053A1

    公开(公告)日：2020-05-14

    申请号：US16384319

    申请日：2019-04-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Uhn CHA ,  Nam-Sung KIM ,  Kyo-Min SOHN

    IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  G11C29/44

    Abstract: Semiconductor memory device includes a memory cell array and an interface circuit including an ECC engine. The memory cell array includes a normal cell region and a parity cell region including a first sub parity region and a second sub parity region. The interface circuit receives main data and sub data comprising external parity or a data mask signal, generates a flag signal based on mask bits of the data mask signal, performs ECC encoding operation on the main data in response to an operation mode and the flag signal, stores the main data in the normal cell region, stores either the external parity or the flag signal in the second sub parity region in response to the operation mode, performs an ECC decoding operation on the main data read from the normal cell region in response to the operation mode and the flag signal.

    MEMORY DEVICE, AND MEMORY SYSTEM INCLUDING THE SAME
    10.
    发明申请
    MEMORY DEVICE, AND MEMORY SYSTEM INCLUDING THE SAME 有权
    存储器件和包括其的存储器系统

    公开(公告)号：US20160071561A1

    公开(公告)日：2016-03-10

    申请号：US14801707

    申请日：2015-07-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Tae-Yoon LEE ,  Myeong-O KIM ,  Kyo-Min SOHN ,  Sang-Joon HWANG

    IPC: G11C7/12 ,  G11C7/22 ,  G11C7/06

    CPC classification number: G11C7/12 ,  G11C11/4076 ,  G11C11/4094

    Abstract: A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to receive an active command after receiving a pre-charge command for a first bank, determine whether or not a pre-charge operation for the first bank has ended when receiving the active command, and generate an active instruction signal according to a result of the determination. The active control circuit may be configured to generate an active control signal for an active operation according to the active instruction signal. The driver circuit may be configured to control an active operation according to the active control signal.

    Abstract translation: 存储器件可以包括预充电控制电路，有源控制电路和驱动器电路。 预充电控制电路可以被配置为在接收到用于第一组的预充电命令之后接收有效命令，确定在接收到活动命令时第一组的预充电操作是否已经结束，并且生成 根据确定的结果激活指令信号。 有源控制电路可以被配置为根据有效指令信号产生用于有效操作的有效控制信号。 驱动器电路可以被配置为根据主动控制信号来控制有效操作。

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