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公开(公告)号:US11631437B2
公开(公告)日:2023-04-18
申请号:US17344235
申请日:2021-06-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Gyuchae Lee , Kyudong Lee
IPC: G11C5/06 , G11C5/04 , G11C16/30 , G11C16/10 , G11C11/4074
Abstract: A memory module is provided including a plurality of semiconductor memory devices mounted on a circuit board. A control device is mounted on the circuit board and configured to receive a command signal, an address signal, and a clock signal and to provide the command signal, the address signal, and the clock signal to the plurality of semiconductor memory devices. A first group of the semiconductor memory devices is disposed between the control device and a first edge portion of the circuit board, and a second group of the semiconductor memory devices is disposed between the control device and a second edge portion of the circuit board. The control device is configured to transmit the address signal to the first group of the semiconductor memory devices and the second group of the semiconductor memory devices through a first transmission line and a second transmission line, respectively. The first transmission line and the second transmission line are physically symmetric with respect to an axis intersecting the control device.
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公开(公告)号:US20200342917A1
公开(公告)日:2020-10-29
申请号:US16709984
申请日:2019-12-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyudong Lee , Young Yun , Sungjoo Park , Jinseong Yun
IPC: G11C5/14
Abstract: A memory module includes a serial presence detector (SPD) configured to detect a module identification (ID) through at least one module position identification terminal, and generate at least one of the module ID and a register address corresponding to the module ID. A power management unit (PMU) is responsive to at least one of the module ID and the register address generated by the SPD. The PMU is configured to set an on-time point and/or an off-time point of an internal clock signal based on at least one of the module ID and the register address corresponding to the module ID, and further configured to generate at least one internal power supply voltage in response to the internal clock signal. A plurality of memory devices are also provided, which are configured to receive the at least one internal power supply voltage and perform an operation in response to command/address signals.
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公开(公告)号:US20200335140A1
公开(公告)日:2020-10-22
申请号:US16727066
申请日:2019-12-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yoo-Jeong Kwon , Jinseong Yun , Kyudong Lee
Abstract: A semiconductor memory module includes a memory printed circuit board (PCB) that includes first connectors, a second connector, and a third connector configured to be connectable with an external device, memory devices that are mounted on the memory PCB and are connected with the first connectors, and a power management integrated circuit that is mounted on the memory PCB, receives a first voltage through the second connector, generates a second voltage from the first voltage, and supplies the second voltage to the memory devices. The power management integrated circuit adjusts the second voltage depending on a difference between a signal received through the third connector and the second voltage.
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公开(公告)号:US20230035640A1
公开(公告)日:2023-02-02
申请号:US17938780
申请日:2022-10-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyudong Lee , Young Yun , Sungjoo Park , Jinseong Yun
IPC: G11C5/14
Abstract: A memory module includes a serial presence detector (SPD) configured to detect a module identification (ID) through at least one module position identification terminal, and generate at least one of the module ID and a register address corresponding to the module ID. A power management unit (PMU) is responsive to at least one of the module ID and the register address generated by the SPD. The PMU is configured to set an on-time point and/or an off-time point of an internal clock signal based on at least one of the module ID and the register address corresponding to the module ID, and further configured to generate at least one internal power supply voltage in response to the internal clock signal. A plurality of memory devices are also provided, which are configured to receive the at least one internal power supply voltage and perform an operation in response to command/address signals.
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公开(公告)号:US11043246B2
公开(公告)日:2021-06-22
申请号:US16733803
申请日:2020-01-03
Applicant: SAMSUNG ELECTRONICS CO., LTD
Inventor: Gyuchae Lee , Kyudong Lee
IPC: G11C5/06 , G11C5/04 , G11C16/30 , G11C16/10 , G11C11/4074
Abstract: A memory module is provided including a plurality of semiconductor memory devices mounted on a circuit board. A control device is mounted on the circuit board and configured to receive a command signal, an address signal, and a clock signal and to provide the command signal, the address signal, and the clock signal to the plurality of semiconductor memory devices. A first group of the semiconductor memory devices is disposed between the control device and a first edge portion of the circuit board, and a second group of the semiconductor memory devices is disposed between the control device and a second edge portion of the circuit board. The control device is configured to transmit the address signal to the first group of the semiconductor memory devices and the second group of the semiconductor memory devices through a first transmission line and a second transmission line, respectively. The first transmission line and the second transmission line are physically symmetric with respect to an axis intersecting the control device.
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公开(公告)号:US12027225B2
公开(公告)日:2024-07-02
申请号:US18109338
申请日:2023-02-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Gyuchae Lee , Kyudong Lee
IPC: G11C5/06 , G11C5/04 , G11C11/4074 , G11C16/10 , G11C16/30
CPC classification number: G11C5/04 , G11C11/4074 , G11C16/10 , G11C16/30
Abstract: A memory module is provided including a plurality of semiconductor memory devices mounted on a circuit board. A control device is mounted on the circuit board and configured to receive a command signal, an address signal, and a clock signal and to provide the command signal, the address signal, and the clock signal to the plurality of semiconductor memory devices. A first group of the semiconductor memory devices is disposed between the control device and a first edge portion of the circuit board, and a second group of the semiconductor memory devices is disposed between the control device and a second edge portion of the circuit board. The control device is configured to transmit the address signal to the first group of the semiconductor memory devices and the second group of the semiconductor memory devices through a first transmission line and a second transmission line, respectively. The first transmission line and the second transmission line are physically symmetric with respect to an axis intersecting the control device.
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公开(公告)号:US11635779B2
公开(公告)日:2023-04-25
申请号:US17358123
申请日:2021-06-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jinseong Yun , Kyudong Lee , Jaejun Lee
IPC: G11C11/4074 , G05F1/575 , G06F1/28 , G11C11/4076 , G11C11/4093
Abstract: A power management integrated circuit (PMIC) includes a voltage regulator, a monitoring circuit, and a count register. The voltage regulator is configured to generate an output voltage. The monitoring circuit is configured to receive a feedback voltage of the output voltage, and to determine at each of periodic intervals whether the feedback voltage is outside a threshold voltage range. The count register is configured to store a count value indicative of a number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range.
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公开(公告)号:US11079784B2
公开(公告)日:2021-08-03
申请号:US16801221
申请日:2020-02-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jinseong Yun , Kyudong Lee , Jaejun Lee
IPC: G11C5/14 , G05F1/575 , G11C11/4074 , G06F1/28 , G11C11/4076 , G11C11/4093
Abstract: A power management integrated circuit (PMIC) includes a voltage regulator, a monitoring circuit, and a count register. The voltage regulator is configured to generate an output voltage. The monitoring circuit is configured to receive a feedback voltage of the output voltage, and to determine at each of periodic intervals whether the feedback voltage is outside a threshold voltage range. The count register is configured to store a count value indicative of a number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range.
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公开(公告)号:US10998012B2
公开(公告)日:2021-05-04
申请号:US16727066
申请日:2019-12-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yoo-Jeong Kwon , Jinseong Yun , Kyudong Lee
Abstract: A semiconductor memory module includes a memory printed circuit board (PCB) that includes first connectors, a second connector, and a third connector configured to be connectable with an external device, memory devices that are mounted on the memory PCB and are connected with the first connectors, and a power management integrated circuit that is mounted on the memory PCB, receives a first voltage through the second connector, generates a second voltage from the first voltage, and supplies the second voltage to the memory devices. The power management integrated circuit adjusts the second voltage depending on a difference between a signal received through the third connector and the second voltage.
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公开(公告)号:US10916274B2
公开(公告)日:2021-02-09
申请号:US16731908
申请日:2019-12-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jong-Geon Lee , Kyudong Lee , Jinseong Yun
IPC: G11C5/14 , G11C5/04 , G06F1/3234 , G06F1/3225
Abstract: A power management integrated circuit includes first pads, second pads, a third pad, and a fourth pad that are configured to be connected with an external device, a regulation block that receives first voltages from the first pads, converts the first voltages to second voltages, and outputs the second voltages to the second pads, a communication block that receives a command through the third pad and outputs an internal information request received together with the command responsive to the command, and a logic block that controls an operation of the regulation block, receives the internal information request from the communication block, and outputs internal state information to the fourth pad based on the internal information request.
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