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1.发明申请Circuit Board, Method for Fabricating the Same and Semiconductor Package Using the Same 有权电路板，其制造方法和使用其的半导体封装公开(公告)号：US20130200531A1
公开(公告)日：2013-08-08
申请号：US13674331
申请日：2012-11-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bok-Sik Myung , Chul-Woo Kim , Kyung-Tae Na , Young-Bae Kim , Yong-Hoon Kim , Hee-Seok Lee
CPC classification number: H05K1/0298 , H01L23/28 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/105 , H01L2224/131 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H05K1/02 , H05K3/4602 , H05K3/4644 , H05K2201/0191 , H05K2201/09136 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2924/00
Abstract: A circuit board is provided including a core insulation film having a thickness and including a first surface and an opposite second surface, an upper stack structure and a lower stack structure. The upper stack structure has a thickness and has an upper conductive pattern having a thickness and an overlying upper insulation film stacked on the first surface of the core insulation film. The lower stack structure has a thickness and has a lower conductive pattern having a thickness and an overlying lower insulation film stacked on the second surface of the core insulation film. A ratio P of a sum of the thicknesses of the upper conductive pattern and the lower conductive pattern to a sum of the thicknesses of the core insulation film, the upper stack structure and the lower stack structure is in a range from about 0.05 to about 0.2.
Abstract translation: 提供一种电路板，包括具有厚度并包括第一表面和相对的第二表面的芯绝缘膜，上堆叠结构和下堆叠结构。 上堆叠结构具有厚度并且具有层叠在芯绝缘膜的第一表面上的厚度的上导电图案和覆盖的上绝缘膜。 下堆叠结构具有厚度并且具有厚度较低的导电图案和堆叠在芯绝缘膜的第二表面上的覆盖的下绝缘膜。 上导电图案和下导电图案的厚度之和与芯绝缘膜，上堆叠结构和下堆叠结构的厚度之和的比率P在约0.05至约0.2的范围内 。
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公开(公告)号：US08970042B2
公开(公告)日：2015-03-03
申请号：US13674331
申请日：2012-11-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bok-Sik Myung , Chul-Woo Kim , Kyung-Tae Na , Young-Bae Kim , Yong-Hoon Kim , Hee-Seok Lee
CPC classification number: H05K1/0298 , H01L23/28 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/105 , H01L2224/131 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H05K1/02 , H05K3/4602 , H05K3/4644 , H05K2201/0191 , H05K2201/09136 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2924/00
Abstract: A circuit board is provided including a core insulation film having a thickness and including a first surface and an opposite second surface, an upper stack structure and a lower stack structure. The upper stack structure has a thickness and has an upper conductive pattern having a thickness and an overlying upper insulation film stacked on the first surface of the core insulation film. The lower stack structure has a thickness and has a lower conductive pattern having a thickness and an overlying lower insulation film stacked on the second surface of the core insulation film. A ratio P of a sum of the thicknesses of the upper conductive pattern and the lower conductive pattern to a sum of the thicknesses of the core insulation film, the upper stack structure and the lower stack structure is in a range from about 0.05 to about 0.2.
Abstract translation: 提供一种电路板，包括具有厚度并包括第一表面和相对的第二表面的芯绝缘膜，上堆叠结构和下堆叠结构。 上堆叠结构具有厚度并且具有层叠在芯绝缘膜的第一表面上的厚度的上导电图案和覆盖的上绝缘膜。 下堆叠结构具有厚度并且具有厚度较低的导电图案和堆叠在芯绝缘膜的第二表面上的覆盖的下绝缘膜。 上导电图案和下导电图案的厚度之和与芯绝缘膜，上堆叠结构和下堆叠结构的厚度之和的比率P在约0.05至约0.2的范围内 。
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