公开(公告)号：US20160126229A1

公开(公告)日：2016-05-05

申请号：US14992174

申请日：2016-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Hoon Kim ,  Hyo-Soon Kang ,  Hee-Seok Lee ,  Jang-Ho Cho

IPC: H01L25/18 ,  H01L23/50 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/18 ,  G11C5/025 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.

Abstract translation: 一种半导体芯片，包括衬底，布置在衬底上的第一数据焊盘和布置在衬底上的第一控制/寻址焊盘，其中第一数据焊盘布置在衬底的边缘区域中，并且第一控制/地址焊盘 布置在基板的中心区域中。

公开(公告)号：US09054067B2

公开(公告)日：2015-06-09

申请号：US14095376

申请日：2013-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Hyoek Im ,  Kyol Park ,  Hee-Seok Lee

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/31 ,  H01L23/427

CPC classification number: H01L23/3733 ,  H01L23/3128 ,  H01L23/3736 ,  H01L23/4275 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A semiconductor package and a method of manufacturing the same are disclosed, wherein the semiconductor package includes a circuit board, a semiconductor chip mounted on the circuit board, an encapsulant positioned on the circuit board and encapsulating the semiconductor chip to the circuit board, and a thermal dissipating member positioned on the encapsulant and having a heat spreader that dissipates a driving heat from the semiconductor chip and a heat capacitor that absorbs excess driving heat that exceeds a heat transfer capability of the heat spreader, such that when a high power is applied to the package, the excess heat is absorbed into the heat capacitor as a latent heat and thus the semiconductor chip is protected from an excessive temperature increase caused by the excess heat, thereby increasing a critical time and performance duration time of the semiconductor package.

Abstract translation: 公开了一种半导体封装及其制造方法，其中半导体封装包括电路板，安装在电路板上的半导体芯片，位于电路板上的密封剂，并将半导体芯片封装在电路板上，以及 散热构件位于密封剂上并具有从半导体芯片散发驱动热量的散热器和吸收超过散热器的传热能力的过量驱动热的热电容器，使得当将高功率施加到 该封装中，多余的热量作为潜热被吸收到热电容器中，因此保护半导体芯片免受由于过量的热量引起的过度的温度升高，从而增加半导体封装的临界时间和性能持续时间。

公开(公告)号：US20130200531A1

公开(公告)日：2013-08-08

申请号：US13674331

申请日：2012-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bok-Sik Myung ,  Chul-Woo Kim ,  Kyung-Tae Na ,  Young-Bae Kim ,  Yong-Hoon Kim ,  Hee-Seok Lee

IPC: H05K1/02 ,  H01L23/28

CPC classification number: H05K1/0298 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H05K1/02 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0191 ,  H05K2201/09136 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A circuit board is provided including a core insulation film having a thickness and including a first surface and an opposite second surface, an upper stack structure and a lower stack structure. The upper stack structure has a thickness and has an upper conductive pattern having a thickness and an overlying upper insulation film stacked on the first surface of the core insulation film. The lower stack structure has a thickness and has a lower conductive pattern having a thickness and an overlying lower insulation film stacked on the second surface of the core insulation film. A ratio P of a sum of the thicknesses of the upper conductive pattern and the lower conductive pattern to a sum of the thicknesses of the core insulation film, the upper stack structure and the lower stack structure is in a range from about 0.05 to about 0.2.

Abstract translation: 提供一种电路板，包括具有厚度并包括第一表面和相对的第二表面的芯绝缘膜，上堆叠结构和下堆叠结构。 上堆叠结构具有厚度并且具有层叠在芯绝缘膜的第一表面上的厚度的上导电图案和覆盖的上绝缘膜。 下堆叠结构具有厚度并且具有厚度较低的导电图案和堆叠在芯绝缘膜的第二表面上的覆盖的下绝缘膜。 上导电图案和下导电图案的厚度之和与芯绝缘膜，上堆叠结构和下堆叠结构的厚度之和的比率P在约0.05至约0.2的范围内 。

公开(公告)号：US09472539B2

公开(公告)日：2016-10-18

申请号：US14992174

申请日：2016-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Hoon Kim ,  Hyo-Soon Kang ,  Hee-Seok Lee ,  Jang-Ho Cho

IPC: H01L23/48 ,  H01L25/18 ,  H01L23/50 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  G11C5/02 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/18 ,  G11C5/025 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.

Abstract translation: 一种半导体芯片，包括衬底，布置在衬底上的第一数据焊盘和布置在衬底上的第一控制/寻址焊盘，其中第一数据焊盘布置在衬底的边缘区域中，并且第一控制/地址焊盘 布置在基板的中心区域中。

公开(公告)号：US09362235B2

公开(公告)日：2016-06-07

申请号：US14173119

申请日：2014-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-hoon Kim ,  Hee-Seok Lee ,  Jin-ha Jeong

IPC: H01L23/552 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L25/03

CPC classification number: H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI).

Abstract translation: 半导体封装包括其中形成有多根导线的基板; 至少一个半导体芯片电连接到多个导线的部分; 并且屏蔽可以安装在基板上，围绕至少一个半导体芯片，电连接到多根导线中的至少一根导线并且包括软磁性材料。 半导体封装可以防止或显着降低电磁干扰（EMI）。

公开(公告)号：US08970042B2

公开(公告)日：2015-03-03

申请号：US13674331

申请日：2012-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bok-Sik Myung ,  Chul-Woo Kim ,  Kyung-Tae Na ,  Young-Bae Kim ,  Yong-Hoon Kim ,  Hee-Seok Lee

IPC: H05K1/02 ,  H01L23/28 ,  H05K3/46 ,  H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC classification number: H05K1/0298 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H05K1/02 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0191 ,  H05K2201/09136 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A circuit board is provided including a core insulation film having a thickness and including a first surface and an opposite second surface, an upper stack structure and a lower stack structure. The upper stack structure has a thickness and has an upper conductive pattern having a thickness and an overlying upper insulation film stacked on the first surface of the core insulation film. The lower stack structure has a thickness and has a lower conductive pattern having a thickness and an overlying lower insulation film stacked on the second surface of the core insulation film. A ratio P of a sum of the thicknesses of the upper conductive pattern and the lower conductive pattern to a sum of the thicknesses of the core insulation film, the upper stack structure and the lower stack structure is in a range from about 0.05 to about 0.2.

Abstract translation: 提供一种电路板，包括具有厚度并包括第一表面和相对的第二表面的芯绝缘膜，上堆叠结构和下堆叠结构。 上堆叠结构具有厚度并且具有层叠在芯绝缘膜的第一表面上的厚度的上导电图案和覆盖的上绝缘膜。 下堆叠结构具有厚度并且具有厚度较低的导电图案和堆叠在芯绝缘膜的第二表面上的覆盖的下绝缘膜。 上导电图案和下导电图案的厚度之和与芯绝缘膜，上堆叠结构和下堆叠结构的厚度之和的比率P在约0.05至约0.2的范围内 。

公开(公告)号：US09520387B2

公开(公告)日：2016-12-13

申请号：US14504972

申请日：2014-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Kim ,  Hee-Seok Lee ,  Seong-Ho Shin ,  Se-Ho You ,  Yun-Hee Lee

IPC: H01L21/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/552 ,  H01L25/10 ,  H01L25/16 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/552 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package.

Abstract translation: 提供堆叠的包装结构。 堆叠封装结构包括：堆叠封装，包括下半导体封装，设置在下半导体封装上并与下半导体封装隔开预定距离的上半导体封装;电连接下半导体封装和 上部半导体封装，同时支撑它们之间的空间，以及绝缘层，其至少设置在所述封装间连接部分的外部并填充所述下部半导体封装和所述上部半导体封装之间的空间，以及围绕所述下部半导体封装的横向和顶部表面的电磁屏蔽层 堆叠包装。

公开(公告)号：US20140217576A1

公开(公告)日：2014-08-07

申请号：US14095376

申请日：2013-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun- Hyoek Im ,  Kyol Park ,  Hee-Seok Lee

IPC: H01L23/367 ,  H01L23/373

CPC classification number: H01L23/3733 ,  H01L23/3128 ,  H01L23/3736 ,  H01L23/4275 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A semiconductor package and a method of manufacturing the same are disclosed, wherein the semiconductor package includes a circuit board, a semiconductor chip mounted on the circuit board, an encapsulant positioned on the circuit board and encapsulating the semiconductor chip to the circuit board, and a thermal dissipating member positioned on the encapsulant and having a heat spreader that dissipates a driving heat from the semiconductor chip and a heat capacitor that absorbs excess driving heat that exceeds a heat transfer capability of the heat spreader, such that when a high power is applied to the package, the excess heat is absorbed into the heat capacitor as a latent heat and thus the semiconductor chip is protected from an excessive temperature increase caused by the excess heat, thereby increasing a critical time and performance duration time of the semiconductor package.

Abstract translation: 公开了一种半导体封装及其制造方法，其中半导体封装包括电路板，安装在电路板上的半导体芯片，位于电路板上的密封剂，并将半导体芯片封装在电路板上，以及 散热构件位于密封剂上并具有从半导体芯片散发驱动热量的散热器和吸收超过散热器的传热能力的过量驱动热的热电容器，使得当将高功率施加到 该封装中，多余的热量作为潜热被吸收到热电容器中，因此保护半导体芯片免受由于过量的热量引起的过度的温度升高，从而增加半导体封装的临界时间和性能持续时间。

公开(公告)号：US20140151859A1

公开(公告)日：2014-06-05

申请号：US14173119

申请日：2014-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-hoon Kim ,  Hee-Seok Lee ,  Jin-ha Jeong

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI).

Abstract translation: 半导体封装包括其中形成有多根导线的基板; 至少一个半导体芯片电连接到多个导线的部分; 并且屏蔽可以安装在基板上，围绕至少一个半导体芯片，电连接到多根导线中的至少一根导线并且包括软磁性材料。 半导体封装可以防止或显着降低电磁干扰（EMI）。