公开(公告)号：US20240064979A1

公开(公告)日：2024-02-22

申请号：US18142191

申请日：2023-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jun Park ,  Kyung Hyun Kim ,  Kun-Woo Park ,  Jun-Youl Yang ,  Dong Woo Lee ,  Sang Hyuk Hong

IPC: H10B43/27 ,  H10B80/00 ,  H10B43/10 ,  H10B43/40 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H01L25/065

CPC classification number: H10B43/27 ,  H10B80/00 ,  H10B43/10 ,  H10B43/40 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H01L25/0652

Abstract: A non-volatile memory device comprises a substrate, a mold structure that includes gate electrodes stacked on the substrate and mold insulating layers alternately stacked with the gate electrodes, a cell contact on the substrate, wherein the cell contact is electrically connected to a selection gate electrode of the gate electrodes and is not electrically connected to a non-selection gate electrode of the gate electrodes, an insulating ring on the substrate, wherein the insulating ring is between the non-selection gate electrode and a sidewall of the cell contact and is in contact with the non-selection gate electrode, and a high dielectric constant layer between respective ones of the gate electrodes and the mold insulating layers, wherein the insulating ring includes a first portion that overlaps the high dielectric constant layer in a vertical direction, and a second portion that does not overlap the high dielectric constant layer in the vertical direction.

公开(公告)号：US09576955B2

公开(公告)日：2017-02-21

申请号：US14992683

申请日：2016-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hwan Lee ,  Tae Yong Kwon ,  Sang Su Kim ,  Chang Jae Yang ,  Jung Han Lee ,  Hwan Wook Choi ,  Yeon Cheol Heo ,  Sang Hyuk Hong

IPC: H01L21/84 ,  H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7849

Abstract: Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.

Abstract translation: 提供半导体器件。 半导体器件包括活性鳍片，其包括设置在衬底上的缓冲层和设置在缓冲层上并具有高于缓冲层的晶格常数的第一晶格常数的沟道层，栅极结构覆盖沟道层并与 设置在栅极结构的两个侧壁上的活动翅片，侧壁间隔物以及设置成接触侧壁间隔物的下表面并具有与侧壁间隔物的下表面的宽度基本相同的宽度的封盖层。