公开(公告)号：US20160055286A1

公开(公告)日：2016-02-25

申请号：US14820983

申请日：2015-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Tae-joong Song ,  Sang-kyu Oh ,  Seung-young Lee

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G03F1/00 ,  G06F17/5072 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

Abstract: A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced.

Abstract translation: 设计集成芯片（IC）的布局的方法包括通过放置和布线定义IC的多个标准单元来设计第一布局，以及通过在与...相关的掩模数据准备处理过程中修改第一布局来生成第二布局 第一布局，其中通过连接与第一布局的第一层相对应的第一层图案中的第一和第二图案来生成第二布局，使得形成第一层图案所需的掩模的数量减少。

公开(公告)号：US09716106B2

公开(公告)日：2017-07-25

申请号：US15232223

申请日：2016-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Sang-kyu Oh ,  Jung-Ho Do ,  Sun-young Park ,  Seung-young Lee ,  Hyo-sig Won

IPC: H01L27/118 ,  H01L27/02 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/42384 ,  H01L29/6681 ,  H01L29/785 ,  H01L2027/11875

Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

公开(公告)号：US20160351583A1

公开(公告)日：2016-12-01

申请号：US15232223

申请日：2016-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon BAEK ,  Sang-kyu Oh ,  Jung-Ho Do ,  Sun-young Park ,  Seung-young Lee ,  Hyo-sig Won

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/42384 ,  H01L29/6681 ,  H01L29/785 ,  H01L2027/11875

Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

Abstract translation: 集成电路（IC）可以包括至少一个单元，其包括在垂直于第一方向的第二方向上在第一方向上延伸并彼此平行的多条导线，第一触点分别设置在两侧 的至少一条导线，以及设置在所述至少一个导电线上的第二触点，并且所述第一触点通过电连接到所述至少一个导线和所述第一触点而形成单个节点 。

公开(公告)号：US09436792B2

公开(公告)日：2016-09-06

申请号：US14820983

申请日：2015-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Tae-joong Song ,  Sang-kyu Oh ,  Seung-young Lee

IPC: G06F17/50 ,  G06F19/00 ,  G21K5/00 ,  G03F1/00

CPC classification number: G06F17/5077 ,  G03F1/00 ,  G06F17/5072 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

Abstract: A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced.

Abstract translation: 设计集成芯片（IC）的布局的方法包括通过放置和布线定义IC的多个标准单元来设计第一布局，以及通过在与...相关的掩模数据准备处理过程中修改第一布局来生成第二布局 第一布局，其中通过连接与第一布局的第一层相对应的第一层图案中的第一和第二图案来生成第二布局，使得形成第一层图案所需的掩模的数量减少。

公开(公告)号：US09478536B2

公开(公告)日：2016-10-25

申请号：US14962401

申请日：2015-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang-hyun Baek ,  Sang-kyu Oh ,  Yongwoo Jeon

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device with fin capacitors is disclosed. The device includes a substrate including a first region and a second region; first and second active fins at the first and second regions, respectively, of the substrate; a device isolation layer in a first trench between the first active fins; first and second gate electrodes that cross the first and second active fins, respectively; a first dielectric layer between the first active fins and the first gate electrode to extend along the first gate electrode, and a second dielectric layer between the second active fins and the second gate electrode to extend along the second gate electrode. The first dielectric layer is spaced apart from a bottom surface of the first trench by the device isolation layer between the bottom surface of the first trench and the first dielectric layer. The second dielectric layer is in direct contact with a bottom surface of a second trench between the second active fins.

Abstract translation: 公开了一种具有散热片电容器的半导体器件。 该装置包括：包括第一区域和第二区域的基板; 分别在基板的第一和第二区域的第一和第二活性散热片; 在所述第一活性鳍片之间的第一沟槽中的器件隔离层; 分别与第一和第二活性鳍片交叉的第一和第二栅极电极; 在所述第一活性鳍片和所述第一栅电极之间沿着所述第一栅电极延伸的第一介电层，以及在所述第二活性鳍片和所述第二栅极之间延伸的第二介电层，以沿着所述第二栅电极延伸。 第一电介质层通过第一沟槽的底表面和第一介电层之间的器件隔离层与第一沟槽的底表面间隔开。 第二电介质层与第二活性鳍片之间的第二沟槽的底表面直接接触。

公开(公告)号：US09837437B2

公开(公告)日：2017-12-05

申请号：US15612349

申请日：2017-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon Baek ,  Sang-kyu Oh ,  Jung-Ho Do ,  Sun-young Park ,  Seung-young Lee ,  Hyo-sig Won

IPC: H01L27/118 ,  H01L29/78 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/42384 ,  H01L29/6681 ,  H01L29/785 ,  H01L2027/11875

Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

公开(公告)号：US09830415B2

公开(公告)日：2017-11-28

申请号：US14799750

申请日：2015-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-kyu Oh ,  Sang-hoon Baek ,  Seung-young Lee ,  Tae-joong Song

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/82

Abstract: A method of designing a semiconductor integrated circuit (IC) is provided as follows. A standard cell library is generated. The standard cell library includes characteristic information for a plurality of standard cells. The characteristic information includes a characteristic of each standard cell. A characteristic change region is detected. The characteristic change region includes at least one of the plurality of standard cells by comparing characteristics of standard cells to be placed adjacent to the characteristic change region, based on the standard cell library. A characteristic of the at least one standard cell included in the detected characteristic change region is changed to one of the characteristics of the standard cells to be placed adjacent to the characteristic change region to update the standard cell library. A plurality of standard cells of the updated standard cell library is placed.