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公开(公告)号：US20220216186A1
公开(公告)日：2022-07-07
申请号：US17705872
申请日：2022-03-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanguk Han , Chajea Jo , Hyoeun Kim , Sunkyoung Seo
IPC: H01L25/065 , H01L23/00 , H01L23/31
Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.
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公开(公告)号：US20240395747A1
公开(公告)日：2024-11-28
申请号：US18638757
申请日：2024-04-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaekul Lee , Hyungsun Jang , Sanguk Han , Taehun Kim
IPC: H01L23/00
Abstract: A semiconductor package may include a semiconductor chip having a first surface and a second surface opposite to the first surface and having a plurality of circuit patterns provided in the second surface, a redistribution wiring layer on the second surface of the semiconductor chip and having a plurality of redistribution wirings and a plurality of bonding pads, the redistribution wirings being electrically connected to the circuit patterns, the bonding pads electrically connected to the redistribution wirings and exposed from a lower surface, a plurality of conductive bumps on the plurality of bonding pads, respectively, and a plurality of spacers on the lower surface of the redistribution wiring layer and configured to align the plurality of conductive bumps through respective through holes of a test socket and to space the redistribution wiring layer from the test socket.
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3.发明授权公开(公告)号：US12148337B2
公开(公告)日：2024-11-19
申请号：US17679587
申请日：2022-02-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sanguk Han , Jaemin Jung , Jeongkyu Ha , Kwanjai Lee
IPC: H01L23/532 , G09G3/20 , H01L23/00
Abstract: A chip on film package is provided. The chip on film package includes a film substrate with a base film, a conductive pad extending in a first direction on the base film, and a conductive line pattern extending from the conductive pad; a semiconductor chip provided on the film substrate; and a bump structure provided between the semiconductor chip and the conductive pad. A first peripheral wall and a second peripheral wall of the bump structure extend in the first direction and define a trench, a portion of the conductive pad is provided in the trench, and the conductive pad is spaced apart from at least one of the first peripheral wall and the second peripheral wall.
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公开(公告)号：US20220139799A1
公开(公告)日：2022-05-05
申请号：US17508483
申请日：2021-10-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaemin Jung , Sanguk Han , Yoonha Jung
IPC: H01L23/373 , H01L23/498 , H01L25/18 , H05K1/18 , H05K1/02
Abstract: A chip-on-film package includes a base film including an upper surface and a lower surface that opposite from each other, a semiconductor chip mounted on the upper surface of the base film, a heat emission layer disposed on the lower surface of the base film to at least partially overlap the semiconductor chip in a thickness direction, an insulating layer disposed on a lower surface of the heat emission layer, and a protective layer surrounding side and lower surfaces of the insulating layer. Accordingly, thermal fatigue of the chip-on-film package may be reduced, and reliability may be increased.
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公开(公告)号：US20240404955A1
公开(公告)日：2024-12-05
申请号：US18800320
申请日：2024-08-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunkyoung SEO , Taehwan Kim , Hyunjung Song , Hyoeun Kim , Wonil Lee , Sanguk Han
IPC: H01L23/538 , H01L23/00 , H01L23/367
Abstract: A semiconductor package includes a redistribution structure, a lower semiconductor device arranged on the redistribution structure and including first through electrodes each having a first horizontal width, a connecting substrate arranged on the redistribution structure and spaced apart from the lower semiconductor device in a horizontal direction and including second through electrodes each having a second horizontal width greater than the first horizontal width, a first molding layer arranged on the redistribution structure and surrounding a side surface of the lower semiconductor device and a side surface of the connecting substrate, and an upper semiconductor device arranged on the lower semiconductor device and the connecting substrate, the upper semiconductor device electrically connected to the first and second through electrodes. A plane area of the upper semiconductor device is greater than a plane area of the lower semiconductor device, and the first horizontal width is about 1 μm to about 7 μm and the second horizontal width is about 10 μm to about 20 μm.
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Patent Agency Ranking
公开(公告)号：US11842945B2
公开(公告)日：2023-12-12
申请号：US17508483
申请日：2021-10-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaemin Jung , Sanguk Han , Yoonha Jung
IPC: H01L25/18 , H01L23/373 , H01L23/498 , H05K1/18 , H05K1/02 , H01L23/00 , H05K1/14
CPC classification number: H01L23/3735 , H01L23/3733 , H01L23/3737 , H01L23/4985 , H01L25/18 , H05K1/0204 , H05K1/189 , H01L24/16 , H01L24/73 , H01L2224/16227 , H01L2224/73204 , H05K1/147 , H05K2201/10128
Abstract: A chip-on-film package includes a base film including an upper surface and a lower surface that opposite from each other, a semiconductor chip mounted on the upper surface of the base film, a heat emission layer disposed on the lower surface of the base film to at least partially overlap the semiconductor chip in a thickness direction, an insulating layer disposed on a lower surface of the heat emission layer, and a protective layer surrounding side and lower surfaces of the insulating layer. Accordingly, thermal fatigue of the chip-on-film package may be reduced, and reliability may be increased.
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公开(公告)号：US11444060B2
公开(公告)日：2022-09-13
申请号：US16742341
申请日：2020-01-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanguk Han , Chajea Jo , Hyoeun Kim , Sunkyoung Seo
IPC: H01L25/065 , H01L23/00 , H01L23/31
Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.
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公开(公告)号：US11328966B2
公开(公告)日：2022-05-10
申请号：US16749620
申请日：2020-01-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyoeun Kim , Yonghoe Cho , Sunkyoung Seo , Seunghoon Yeon , Sanguk Han
Abstract: A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.
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公开(公告)号：US20240142493A1
公开(公告)日：2024-05-02
申请号：US18497401
申请日：2023-10-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanguk Han , Jaekul Lee , Hyungsun Jang , Taehun Kim
CPC classification number: G01R1/0466 , G01R31/2863 , H01L24/13 , H01L24/29 , H01L2224/13006 , H01L2224/29022
Abstract: A socket for testing a semiconductor package includes a body having an internal space configured to accommodate a semiconductor package; and at least a first spacer on the body and positioned to contact a first surface of the semiconductor package when the semiconductor package is placed on the body. The body includes a lower socket portion provided with through-holes, configured through which to receive meter reading pins that contact external connection terminals of the semiconductor package, and an upper socket portion disposed above the lower socket portion, and the first spacer is disposed on a surface of the lower socket portion that faces the first surface of the semiconductor package when the semiconductor package is placed on the body.
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公开(公告)号：US11869818B2
公开(公告)日：2024-01-09
申请号：US17733411
申请日：2022-04-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyoeun Kim , Yonghoe Cho , Sunkyoung Seo , Seunghoon Yeon , Sanguk Han
CPC classification number: H01L22/32 , G01R27/2605 , G01R31/2818 , H01L22/14 , H01L23/3128 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2225/06513
Abstract: A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.
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