公开(公告)号：US20220149040A1

公开(公告)日：2022-05-12

申请号：US17584877

申请日：2022-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryul LEE ,  Yongseung KIM ,  Jungtaek KIM ,  Pankwi PARK ,  Dongchan SUH ,  Moonseung YANG ,  Seojin JEONG ,  Minhee CHOI ,  Ryong HA

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.

公开(公告)号：US20210408241A1

公开(公告)日：2021-12-30

申请号：US17471244

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seojin JEONG ,  Jinyeong JOE ,  Seokhoon KIM ,  Jeongho YOO ,  Seung Hun LEE ,  Sihyung LEE

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/04 ,  H01L29/167 ,  H01L29/36 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

公开(公告)号：US20230395661A1

公开(公告)日：2023-12-07

申请号：US18149957

申请日：2023-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sumin YU ,  Jungtaek KIM ,  Moonseung YANG ,  Seojin JEONG ,  Edward CHO ,  Seokhoon KIM ,  Pankwi PARK

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66439 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/42392

Abstract: An integrated circuit (IC) device including fin-type active regions parallel to each other on a substrate, the fin-type active regions extending in a first lateral direction, a first nanosheet stack apart from a fin top surface of a first fin-type active region selected from the fin-type active regions, the first nanosheet stack including at least one nanosheet facing the fin top surface of the first fin-type active region, a gate structure surrounding the first nanosheet stack, the gate structure extending in a second lateral direction, a first source/drain region in contact with one sidewall of the first nanosheet stack, and a second source/drain region in contact with another sidewall of the first nanosheet stack , wherein a greatest width of the first source/drain region is less than a greatest width of the second source/drain region in the second lateral direction may be provided.

公开(公告)号：US20210082914A1

公开(公告)日：2021-03-18

申请号：US16841806

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryul LEE ,  Yongseung KIM ,  Jungtaek KIM ,  Pankwi PARK ,  Dongchan SUH ,  Moonseung YANG ,  Seojin JEONG ,  Minhee CHOI ,  Ryong HA

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.