Abstract:
A computing system is disclosed. The computing system according to one embodiment of the present disclosure comprises: a memory device for storing an application program; a processor for executing a loader for loading data of the application program into a memory space allocated for execution of the application program; a local memory having a width corresponding to the size of a register of the processor; and a constant memory having a width smaller than that of the local memory, wherein, according to the size of constant data included in the application program, the processor loads the constant data into one of the local memory and the constant memory.
Abstract:
An electronic apparatus for performing machine learning a method of machine learning, and a non-transitory computer-readable recording medium are provided. The electronic apparatus includes an operation module configured to include a plurality of processing elements arranged in a predetermined pattern and share data between the plurality of processing elements which are adjacent to each other to perform an operation; and a processor configured to control the operation module to perform a convolution operation by applying a filter to input data, wherein the processor controls the operation module to perform the convolution operation by inputting each of a plurality of elements configuring a two-dimensional filter to the plurality of processing elements in a predetermined order and sequentially applying the plurality of elements to the input data.
Abstract:
Provided are a storage device and a method of distributed processing of multimedia data. In the method, the storage device stores multimedia data, initiates an interface configured to share data between a host and the storage device, receives a multimedia data request from the host, processes the multimedia data based on the received multimedia data request, and transmits the processed multimedia data to the host through the interface.
Abstract:
A processor and a control method thereof are processed. The processor includes an instruction fetch module configured to receive a first instruction of an interrupt service routine without backup of data stored in a register in response to processing of the interrupt service routine being requested, a detecting module configured to analyze the received first instruction to determine whether the data stored in the register needs to be changed, an instruction generating module configured to generate a second instruction for storing data in a temporary memory when the stored data is initially changed, an instruction selecting module configured to sequentially select the generated second instruction and first instruction; and a control module configured to perform the second instruction and the first instruction.
Abstract:
Provided are a reconfigurable processor and a method of operating the same, the reconfigurable processor including: a configurable memory configured to receive a task execution instruction from a control processor; and a plurality of reconfigurable arrays, each configured to receive configuration information from the configurable memory, wherein each of the plurality of reconfigurable arrays simultaneously executes a task based on the configuration information.
Abstract:
A method of preventing a bank conflict in a memory includes determining processing timing of each of threads of function units to access a first memory bank in which occurrence of a bank conflict is expected, setting a variable latency of each of the threads for sequential access of the threads according to the determined processing timing, sequentially storing the threads in a data memory queue according to the determined processing timing, and performing an operation by allowing the threads stored in the data memory queue to sequentially access the first memory bank whenever the variable latency of each of the threads passes.
Abstract:
A method of executing, by a processor, a multi-thread including threads of the processor, includes setting a mask value indicating execution of one of the threads of the processor based on an instruction, setting an inverted mask value based on the set mask value; and executing the thread of the processor based on the set mask value and the set inverted mask value.
Abstract:
An electronic apparatus includes a first body which includes a keyboard and an adaptor, and a second body which includes a display and a frame in which the display is installed. The first body includes a first magnet, and the second body includes a second magnet. The second body is rotatable with respect to the keyboard of the first body while the first body is attached to the second body.
Abstract:
A modulo scheduling method including calculating at least two candidate initiation intervals between adjacent iterations, searching for schedules of the instructions in parallel by using the candidate initiation intervals, and selecting a schedule determined to be valid from among the searched schedules.
Abstract:
An apparatus comprises a first body including a display and a second body including a first portion and a second portion, the first portion including an input device to receive an input, and the second portion including a magnet to magnetically attach to the first body. An apparatus comprises a body having a display screen, and having a frame with a first surface having an opening to expose the display screen, a second surface disposed opposite to the first surface, and a side portion disposed between the first surface and the second surface and having one or more magnets disposed in the side portion of the frame of the body.