公开(公告)号：US20230335618A1

公开(公告)日：2023-10-19

申请号：US17989936

申请日：2022-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chankyo PARK ,  Seungchul OH ,  Jaeho JEON ,  Sunggi HUR

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/66545 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/66742 ,  H01L29/66439

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming, on a substrate, dummy gate structures extending in a first direction, spaced apart from one another along a second direction, forming a first oxide layer on the dummy gate structures, etching an upper portion of the first oxide layer and the dummy gate to form a recess region, providing a first nitride layer in the recessed region, forming a second oxide layer on the first nitride layer and the first oxide layer, partially removing upper portions of the first oxide layer and the second oxide layer and providing a second nitride layer on the first and second oxide layers.

公开(公告)号：US20190333823A1

公开(公告)日：2019-10-31

申请号：US16503728

申请日：2019-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk LEE ,  JEONGYUN LEE ,  Yongseok LEE ,  Bosoon KIM ,  SANGDUK PARK ,  Seungchul OH ,  YOUNGMOOK OH

IPC: H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L21/762

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US20240145326A1

公开(公告)日：2024-05-02

申请号：US18323680

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchul OH ,  Junwoo MYUNG ,  Jangbae SON ,  Gun LEE

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/3128 ,  H01L21/568 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

Abstract: A method of manufacturing a semiconductor package includes adding an insulating frame to a surface of a carrier substrate, wherein the insulating frame covers a side surface of a first metal layer on the surface of the carrier substrate and bringing a cover insulating layer into contact with the insulating frame and the first metal layer, wherein the cover insulating layer covers at least one semiconductor chip.

公开(公告)号：US20220122891A1

公开(公告)日：2022-04-21

申请号：US17562802

申请日：2021-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk LEE ,  JEONGYUN LEE ,  Yongseok LEE ,  Bosoon KIM ,  SANGDUK PARK ,  Seungchul OH ,  YOUNGMOOK OH

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/08

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US20170200651A1

公开(公告)日：2017-07-13

申请号：US15405420

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk LEE ,  JEONGYUN LEE ,  Yongseok LEE ,  Bosoon KIM ,  SANGDUK PARK ,  Seungchul OH ,  YOUNGMOOK OH

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.