公开(公告)号：US12218043B2

公开(公告)日：2025-02-04

申请号：US17971321

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yukyung Park ,  Ungcheon Kim ,  Sungwoo Park ,  Seungkwan Ryu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/18 ,  H01L23/544

Abstract: Provided is an interposer for a semiconductor package, the interposer including an interposer substrate comprising a first main surface and a second main surface opposite to the first main surface, a first through-electrode structure and a second through-electrode structure each passing through the interposer substrate and protruding from the first main surface, a connection terminal structure contacting both the first through-electrode structure and the second through-electrode structure, and a photosensitive polymer layer arranged between the connection terminal structure and the interposer substrate, and between the first through-electrode structure and the second through-electrode structure.

公开(公告)号：US11848307B2

公开(公告)日：2023-12-19

申请号：US17478247

申请日：2021-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Park ,  Ungcheon Kim ,  Heonwoo Kim ,  Yunseok Choi

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/562

Abstract: A semiconductor package includes a base substrate and an interposer substrate. The interposer substrate includes a semiconductor substrate, a first passivation layer, a wiring region, a through via penetrating through the semiconductor substrate and the first passivation layer, and a second passivation layer covering at least a portion of the first passivation layer and having an opening exposing a lower surface of the through via. The semiconductor package further includes a conductive pillar extending from the opening of the second passivation layer; and a conductive bump disposed between the conductive pillar and the base substrate. The opening of the second passivation layer has inclined side surfaces such that a width of the opening decreases towards the first passivation layer, and side surfaces of the conductive pillar are positioned to overlap the inclined side surfaces of the second passivation layer in a vertical direction.

公开(公告)号：US20210026249A1

公开(公告)日：2021-01-28

申请号：US16593149

申请日：2019-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/20 ,  G05B19/4097 ,  H01L21/027

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

公开(公告)号：US20250132238A1

公开(公告)日：2025-04-24

申请号：US18991938

申请日：2024-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yukyung Park ,  Ungcheon Kim ,  Sungwoo Park ,  Seungkwan Ryu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/544 ,  H01L25/18

Abstract: Provided is an interposer for a semiconductor package, the interposer including an interposer substrate comprising a first main surface and a second main surface opposite to the first main surface, a first through-electrode structure and a second through-electrode structure each passing through the interposer substrate and protruding from the first main surface, a connection terminal structure contacting both the first through-electrode structure and the second through-electrode structure, and a photosensitive polymer layer arranged between the connection terminal structure and the interposer substrate, and between the first through-electrode structure and the second through-electrode structure.

公开(公告)号：US20230352386A1

公开(公告)日：2023-11-02

申请号：US18347519

申请日：2023-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ungcheon Kim ,  Sungwoo Park ,  Yukyung Park ,  Seungkwan Ryu

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L21/4857 ,  H01L23/49816 ,  H01L25/18

Abstract: An interposer including a base layer, a redistribution structure on a first surface of the base layer and including a conductive redistribution pattern, a first lower protection layer on a second surface of the base layer, a lower conductive pad on the first lower protection layer, a through electrode connecting the conductive redistribution pattern and the lower conductive pad, a second lower protection layer on the first lower protection layer, including a different material than the first lower protection layer, and contacting at least a portion of the lower conductive pad, and an indentation formed in an outer edge region of the interposer to provide a continuous angled sidewall extending entirely through the second lower protection layer and through at least a portion of the first protection layer.

公开(公告)号：US20230052195A1

公开(公告)日：2023-02-16

申请号：US17971321

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yukyung Park ,  Ungcheon Kim ,  Sungwoo Park ,  Seungkwan Ryu

IPC: H01L23/498 ,  H01L25/18 ,  H01L21/48 ,  H01L23/538

Abstract: Provided is an interposer for a semiconductor package, the interposer including an interposer substrate comprising a first main surface and a second main surface opposite to the first main surface, a first through-electrode structure and a second through-electrode structure each passing through the interposer substrate and protruding from the first main surface, a connection terminal structure contacting both the first through-electrode structure and the second through-electrode structure, and a photosensitive polymer layer arranged between the connection terminal structure and the interposer substrate, and between the first through-electrode structure and the second through-electrode structure.

公开(公告)号：US20210175161A1

公开(公告)日：2021-06-10

申请号：US17038306

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yukyung Park ,  Ungcheon Kim ,  Sungwoo Park ,  Seungkwan Ryu

IPC: H01L23/498 ,  H01L25/18 ,  H01L21/48 ,  H01L23/538

Abstract: Provided is an interposer for a semiconductor package, the interposer including an interposer substrate comprising a first main surface and a second main surface opposite to the first main surface, a first through-electrode structure and a second through-electrode structure each passing through the interposer substrate and protruding from the first main surface, a connection terminal structure contacting both the first through-electrode structure and the second through-electrode structure, and a photosensitive polymer layer arranged between the connection terminal structure and the interposer substrate, and between the first through-electrode structure and the second through-electrode structure.

公开(公告)号：US12272630B2

公开(公告)日：2025-04-08

申请号：US18347519

申请日：2023-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ungcheon Kim ,  Sungwoo Park ,  Yukyung Park ,  Seungkwan Ryu

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/18

Abstract: An interposer including a base layer, a redistribution structure on a first surface of the base layer and including a conductive redistribution pattern, a first lower protection layer on a second surface of the base layer, a lower conductive pad on the first lower protection layer, a through electrode connecting the conductive redistribution pattern and the lower conductive pad, a second lower protection layer on the first lower protection layer, including a different material than the first lower protection layer, and contacting at least a portion of the lower conductive pad, and an indentation formed in an outer edge region of the interposer to provide a continuous angled sidewall extending entirely through the second lower protection layer and through at least a portion of the first protection layer.

公开(公告)号：US12119288B2

公开(公告)日：2024-10-15

申请号：US17658614

申请日：2022-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbae Kim ,  Sungwoo Park

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/4951 ,  H01L23/49548 ,  H01L24/16 ,  H01L23/3107 ,  H01L23/49513 ,  H01L24/14 ,  H01L2224/1415 ,  H01L2224/16258

Abstract: A semiconductor package includes: a lead frame that includes a first surface and a second surface opposite to the first surface, where the lead frame includes a first lead that extends in a first direction, and a plurality of second leads that are spaced apart from the first lead on both sides of the first lead; at least one semiconductor chip mounted on the first surface of the lead frame by a plurality of bumps; and an encapsulant that encapsulates the lead frame and the at least one semiconductor chip, wherein the first lead has a groove in the first surface that partitions the plurality of bumps in contact with the first lead.

公开(公告)号：US12080691B2

公开(公告)日：2024-09-03

申请号：US17585122

申请日：2022-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Park ,  Heonwoo Kim ,  Sangcheon Park ,  Wonil Lee

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/37001

Abstract: A semiconductor device including an interposer including a central region and an edge region entirely surrounding the central region, wherein the interposer includes a wiring structure disposed in the first region and a metal structure disposed continuously within the entirety of the second region, a first semiconductor chip mounted in the central region and connected to the wiring structure, and a second semiconductor chip mounted in the central region adjacent to the first semiconductor chip and connected to the second wiring structure.