公开(公告)号：US20170005175A1

公开(公告)日：2017-01-05

申请号：US15186982

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol SONG ,  Wandon KIM ,  Hoonjoo NA ,  Suyoung BAE ,  Hyeok-Jun SON ,  Sangjin HYUN

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L27/085

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may he between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.

Abstract translation: 半导体器件包括半导体衬底，该半导体衬底包括具有共同导电类型的多个有源区和在分离的有源区上分开的相应的栅电极。 不同的高k电介质层可以在分离的有源区和有源区上的相应栅电极之间。 不同数量的高k电介质层可以在分离的有源区域和有源区域上的相应栅电极之间。 不同的高k电介质层可以包括不同的功函调整材料。

公开(公告)号：US20230361121A1

公开(公告)日：2023-11-09

申请号：US18353214

申请日：2023-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo LEE ,  Wonkeun CHUNG ,  Hoonjoo NA ,  Suyoung BAE ,  Jaeyeol SONG ,  Jonghan LEE ,  HyungSuk JUNG ,  Sangjin HYUN

IPC: H01L27/092 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L29/78696 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/42392

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US20210358910A1

公开(公告)日：2021-11-18

申请号：US17384920

申请日：2021-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo LEE ,  Wonkeun CHUNG ,  Hoonjoo NA ,  Suyoung BAE ,  Jaeyeol SONG ,  Jonghan LEE ,  HyungSuk JUNG ,  Sangjin HYUN

IPC: H01L27/092 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US20250063804A1

公开(公告)日：2025-02-20

申请号：US18668920

申请日：2024-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suyoung BAE ,  Ohseong Kwon ,  Jaeyeol Song ,  Jeonghyuk Yim

IPC: H01L21/8238 ,  H01L21/308 ,  H01L27/092

Abstract: Provided is a semiconductor device and method of manufacturing same, the method including: preparing a substrate including first and second regions; forming a first and second channel patterns in the first and second regions, wherein the first and second channel patterns each include a plurality of semiconductor patterns vertically stacked on the substrate, an inner region, and an outer region; forming a high-k dielectric layer covering the first channel pattern and the second channel pattern; forming a first protective mask on the high-k dielectric layer in the first region and the second region; removing the first protective mask from the first outer region and the second outer region; and forming an additional mask layer surrounding the first channel pattern and the second channel pattern, wherein the additional mask layer does not have etch selectivity with the first protective mask.