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1.发明授权Phase locked loop for preventing harmonic lock, method of operating the same, and devices including the same 有权用于防止谐波锁定的锁相环，其操作方法和包括其的装置公开(公告)号：US09525545B2
公开(公告)日：2016-12-20
申请号：US14182029
申请日：2014-02-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woon Taek Oh , Jin Ho Kim , Tae Jin Kim , Jae Youl Lee , Young Hwan Chang
CPC classification number: H04L7/0331 , G09G3/20 , G09G5/02 , G09G2310/0267 , G09G2310/027 , G11C7/1096 , G11C7/222 , H03L7/095 , H04L7/033
Abstract: A phase locked loop includes a voltage controlled oscillator including a plurality of delay cells configured to respectively generate a plurality of clock signals having different phases and a harmonic lock detector configured to detect harmonic lock in the voltage controlled oscillator and to generate a reset signal in response. Remaining ones of the delay cells other than a first delay cell among the plurality of delay cells are reset in response to the reset signal.
Abstract translation: 锁相环包括压控振荡器，其包括被配置为分别产生具有不同相位的多个时钟信号的多个延迟单元和被配置为检测压控振荡器中的谐波锁定并且响应地产生复位信号的谐波锁定检测器 。 多个延迟单元中除第一延迟单元之外的延迟单元的剩余的单元响应于复位信号被复位。
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公开(公告)号：US10698852B2
公开(公告)日：2020-06-30
申请号：US15941607
申请日：2018-03-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tae Jin Kim , Hyun Wook Lim , Seong Young Ryu , Soo Joo Lee
IPC: G06F13/40 , H03K19/0175 , G09G3/20 , G09G5/00
Abstract: A termination circuit is provided. The termination device includes terminals configured to receive a corresponding signal; unit circuits respectively connected to the terminals, the unit circuits each including a unit resistor and a unit switch element connected to each other in series; common mode capacitors; first switch elements respectively connected between each of the unit circuits and a first corresponding common mode capacitor of common mode capacitors, each of the first switch elements being configured to turn on when the corresponding signal is received in a first mode; and second switch elements respectively connected between each of the unit circuits and a second corresponding common mode capacitor of the common mode capacitors, the second switch elements being configured to turn on when the corresponding signal is received in a second mode different from the first mode.
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公开(公告)号：US09432028B2
公开(公告)日：2016-08-30
申请号：US14716106
申请日：2015-05-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tae Jin Kim , Chang Hoon Baek , Sang Kyu Lee , Jae Youl Lee
CPC classification number: H03L7/0807 , H03L1/00 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/093 , H03L7/0992 , H03L7/0995 , H03L7/113 , H03L7/187 , H03L2207/06 , H03L2207/50
Abstract: A clock data recovery circuit including: a digital phase detector and deserializer configured to sample serial data using a recovery clock signal to generate an up phase error signal and a down phase error signal which correspond to a phase difference between the serial data and the recovery clock signal; a digital loop filter configured to generate an up fine code and a down fine code based on a result of counting the up and down phase error signals; a loop combiner configured to generate an up fine tuning code and a down fine tuning code by using the up and down phase error signals and the up and down fine codes; and a digitally controlled oscillator configured to generate the recovery clock signal having a frequency changed with the up and down fine tuning codes.
Abstract translation: 一种时钟数据恢复电路，包括：数字相位检测器和解串器，被配置为使用恢复时钟信号对串行数据进行采样，以产生对应于串行数据和恢复时钟之间的相位差的上相位误差信号和下行相位误差信号 信号; 数字环路滤波器，其被配置为基于对所述上下相位误差信号进行计数的结果来生成上位编码和下精细码; 配置为通过使用上下相位误差信号和上下精细码产生上调微调码和下调微调码的环路组合器; 以及数字控制振荡器，被配置为产生具有随着上下微调代码而改变的频率的恢复时钟信号。
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4.发明申请Phase Locked Loop for Preventing Harmonic Lock, Method of Operating the Same, and Devices Including the Same 有权用于防止谐波锁定的锁相环，其操作方法及包括它的设备公开(公告)号：US20140240371A1
公开(公告)日：2014-08-28
申请号：US14182029
申请日：2014-02-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woon Taek Oh , Jin Ho Kim , Tae Jin Kim , Jae Youl Lee , Young Hwan Chang
CPC classification number: H04L7/0331 , G09G3/20 , G09G5/02 , G09G2310/0267 , G09G2310/027 , G11C7/1096 , G11C7/222 , H03L7/095 , H04L7/033
Abstract: A phase locked loop includes a voltage controlled oscillator including a plurality of delay cells configured to respectively generate a plurality of clock signals having different phases and a harmonic lock detector configured to detect harmonic lock in the voltage controlled oscillator and to generate a reset signal in response. Remaining ones of the delay cells other than a first delay cell among the plurality of delay cells are reset in response to the reset signal.
Abstract translation: 锁相环包括压控振荡器，其包括被配置为分别产生具有不同相位的多个时钟信号的多个延迟单元和被配置为检测压控振荡器中的谐波锁定并且响应地产生复位信号的谐波锁定检测器 。 多个延迟单元中除第一延迟单元之外的延迟单元的剩余的单元响应于复位信号被复位。
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