公开(公告)号：US20150280751A1

公开(公告)日：2015-10-01

申请号：US14224572

申请日：2014-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Iddo NAISS ,  Uri BEITLER ,  Jun Jin KONG

IPC: H03M13/00 ,  H03M13/11 ,  G06F11/10

CPC classification number: H03M13/6312 ,  G06F11/1004 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/152

Abstract: A memory controller includes a joint source-channel encoder circuit and a joint source-channel decoder circuit. The joint source-channel encoder circuit source encodes received data independent of whether the received data is compressible data, performs error correction coding on the source encoded data, and stores the source encoded data in a memory device. The joint source-channel decoder circuit performs source decoding of the data read from the memory device between iterations of error correction coding of the read data, and outputs the read data to at least one of a buffer memory and a storage device interface. The joint source-channel decoder circuit performs the source decoding of the read data independent of whether the read data is compressed data.

Abstract translation: 存储器控制器包括联合源通道编码器电路和联合源通道解码器电路。 联合源信道编码器电路源对接收到的数据进行编码，独立于接收到的数据是否是可压缩数据，对源编码数据执行纠错编码，并将源编码数据存储在存储器件中。 联合源信道解码器电路在读取数据的纠错编码的迭代之间对从存储器件读取的数据执行源解码，并将读取的数据输出到缓冲存储器和存储设备接口中的至少一个。 联合源信道解码器电路执行读取数据的源解码，与读数据是否为压缩数据无关。

公开(公告)号：US20160321135A1

公开(公告)日：2016-11-03

申请号：US14699810

申请日：2015-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Amit BERMAN ,  Uri BEITLER ,  Jun Jin KONG

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/05

CPC classification number: G06F11/1044 ,  G06F11/1012 ,  H03M13/05 ,  H03M13/611

Abstract: A memory device controller includes an error correction processor and a compression processor. The error correction processor is configured to obtain error location information for page data received from a source memory block over a memory channel. The compression processor is configured to compress the obtained error location information, and to output the compressed error location information to a target memory block without the page data over the same memory channel.

Abstract translation: 存储器件控制器包括纠错处理器和压缩处理器。 错误校正处理器被配置为获得通过存储器通道从源存储器块接收的页面数据的错误位置信息。 压缩处理器被配置为压缩获得的错误位置信息，并且将压缩的错误位置信息输出到目标存储器块，而不需要通过同一存储器通道的页数据。

公开(公告)号：US20160291898A1

公开(公告)日：2016-10-06

申请号：US14677588

申请日：2015-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Uri BEITLER ,  Jun Jin KONG

IPC: G06F3/06

CPC classification number: G06F3/0643 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0667 ,  G06F3/0679

Abstract: At least one example embodiment discloses a memory storage device including a first memory and a controller configured to program a file into the first memory, read the file from the first memory upon receiving a request for the file from an external host, the request identifying requested manipulations to the file, and manipulate the file in accordance with the request.

Abstract translation: 至少一个示例实施例公开了一种存储器存储设备，其包括第一存储器和被配置为将文件编程到第一存储器中的控制器，在从外部主机接收到对该文件的请求时从第一存储器读取该文件， 操纵文件，并根据请求操纵文件。

公开(公告)号：US20160371028A1

公开(公告)日：2016-12-22

申请号：US14743445

申请日：2015-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Amit BERMAN ,  Jun Jin KONG ,  Uri BEITLER

IPC: G06F3/06

CPC classification number: G11C11/5642 ,  G06F12/00 ,  G06F12/0246 ,  G06F2212/1024 ,  G06F2212/401 ,  G06F2212/7202 ,  G06F2212/7203 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5641

Abstract: A memory system includes a memory device, the memory device including, a memory cell array, and a compression encoder, the memory cell array including a first plurality of multi level cells (MLCs), the memory device being configured to, generate a first partial page by performing one or more first sensing operation on the first plurality of MLCs using one or more first reference voltages, output the first partial page, generate a second partial page by performing a second sensing operation on the first plurality of MLCs based on a second reference voltage, the second reference voltage having a different voltage level than the one or more first reference voltages, generate a second compressed partial page by compressing the second partial page using the compression encoder, and output the compressed second partial page.

Abstract translation: 存储器系统包括存储器件，存储器件包括存储器单元阵列和压缩编码器，所述存储器单元阵列包括第一多个多电平单元（MLC），所述存储器器件被配置为产生第一部分 通过使用一个或多个第一参考电压对所述第一多个MLC执行一个或多个第一感测操作，输出所述第一部分页面，通过基于第二部分页面对所述第一多个MLC执行第二感测操作来生成第二部分页面 参考电压，具有与所述一个或多个第一参考电压不同的电压电平的所述第二参考电压，通过使用所述压缩编码器压缩所述第二部分页面来生成第二压缩部分页面，并输出所述压缩的第二局部页面。

公开(公告)号：US20150058692A1

公开(公告)日：2015-02-26

申请号：US14334947

申请日：2014-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Amir BENNATAN ,  Avner DOR ,  Moshe TWITTO ,  Guy GABSO ,  Yoav SHERESHEVSKI ,  Uri BEITLER ,  Jun-jin KONG ,  Beom-Kyu SHIN

IPC: H03M13/11

CPC classification number: H03M13/1111 ,  G11B2020/185 ,  H03M13/1131 ,  H03M13/1137 ,  H03M13/6566

Abstract: A low-density parity-check (LDPC) decoding method includes exchanging messages between check nodes and variable nodes based on scheduling information representing an order of exchanging messages between the check nodes and the variable nodes for an LDPC decoding, and performing the LDPC decoding based on the exchanged messages, wherein the scheduling information is determined by manipulating at least one of an order of the check nodes and an order of the variable nodes in an LDPC bipartite graph.

Abstract translation: 低密度奇偶校验（LDPC）解码方法包括基于表示在校验节点和可变节点之间交换消息的顺序的调度信息进行LDPC解码的校验节点和可变节点之间的消息交换，并且基于LDPC解码 在所交换的消息上，其中通过在LDPC二分图中操纵校验节点的顺序和可变节点的顺序中的至少一个来确定调度信息。

公开(公告)号：US20180081754A1

公开(公告)日：2018-03-22

申请号：US15270292

申请日：2016-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Amit BERMAN ,  Uri BEITLER ,  Jun Jin KONG

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/09 ,  H03M13/29

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G06F11/108 ,  G11C29/52 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/37 ,  H03M13/3776 ,  H03M13/6312

Abstract: A memory system includes a data channel, a controller configured to output a request across the data channel, and a memory device configured to store data and corresponding first parity, perform a decoding operation on the data to generate second parity in response to receipt of the request across the data channel, generate a difference from the first parity and the second parity, compress the difference, and enable the controller to access the data and the compressed difference to satisfy the request.

公开(公告)号：US20170017590A1

公开(公告)日：2017-01-19

申请号：US14801241

申请日：2015-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Amit BERMAN ,  Uri BEITLER ,  Jun Jin KONG

IPC: G06F13/28 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0688

Abstract: A memory system includes a first plurality of nonvolatile memory devices of a first channel of the memory system, the first plurality of memory devices each being connected to a first communications bus; a second plurality of nonvolatile memory devices of a second channel of the memory system, the second plurality of memory devices each being connected to a second communications bus, and a first interconnection between a first memory device and a second memory device, the first memory device being a memory device from among the first plurality of nonvolatile memory devices, the second memory device being a memory device from among the second plurality of nonvolatile memory devices.

Abstract translation: 存储器系统包括存储器系统的第一通道的第一多个非易失性存储器件，每个第一多个存储器件连接到第一通信总线; 所述存储器系统的第二通道的第二多个非易失性存储器件，所述第二多个存储器件各自连接到第二通信总线，以及第一存储器件和第二存储器件之间的第一互连，所述第一存储器件 作为来自第一多个非易失性存储器件的存储器件，第二存储器件是第二多个非易失性存储器件中的存储器件。