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公开(公告)号:US10128379B2
公开(公告)日:2018-11-13
申请号:US15647903
申请日:2017-07-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seung Min Song , Woo Seok Park , Geum Jong Bae , Dong Il Bae , Jung Gil Yang
IPC: H01L29/786 , H01L29/06 , H01L29/423 , H01L29/66 , H01L21/02
Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.
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公开(公告)号:US10243040B1
公开(公告)日:2019-03-26
申请号:US15964170
申请日:2018-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Woo Seok Park , Seung Min Song , Jung Gil Yang , Geum Jong Bae , Dong Il Bae
IPC: H01L29/66 , H01L29/06 , H01L29/78 , H01L29/417
Abstract: A semiconductor device including a transistor disposed on a first region of a substrate, the transistor including source/drain regions, a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate while connecting the source/drain regions, respectively, a gate electrode surrounding each of the plurality of channel layers, and a gate insulator between the gate electrode and the plurality of channel layers; and a non-active component disposed on a second region of the substrate, the non-active component including a fin structure including an a plurality of first semiconductor patterns alternately stacked with a plurality of second semiconductor patterns, an epitaxial region adjacent to the fin structure, a non-active electrode intersecting the fin structure, and a blocking insulation film between the non-active electrode and the fin structure.
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公开(公告)号:US20230387237A1
公开(公告)日:2023-11-30
申请号:US18449734
申请日:2023-08-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: MYUNG GIL KANG , Dong Won Kim , Woo Seok Park , Keun Hwi Cho , Sung Gi Hur
IPC: H01L29/423 , H01L27/092 , H01L29/06 , H01L29/786
CPC classification number: H01L29/42392 , H01L27/092 , H01L29/0665 , H01L29/78696 , H01L29/4236
Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.
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公开(公告)号:US10181510B2
公开(公告)日:2019-01-15
申请号:US15726535
申请日:2017-10-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jung Gil Yang , Seung Min Song , Sung Min Kim , Woo Seok Park , Geum Jong Bae , Dong Il Bae
IPC: H01L29/76 , H01L29/06 , H01L29/49 , H01L29/66 , H01L29/786
Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.
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公开(公告)号:US12183800B2
公开(公告)日:2024-12-31
申请号:US18449734
申请日:2023-08-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Myung Gil Kang , Dong Won Kim , Woo Seok Park , Keun Hwi Cho , Sung Gi Hur
IPC: H01L29/423 , H01L27/092 , H01L29/06 , H01L29/786
Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.
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公开(公告)号:US20240421212A1
公开(公告)日:2024-12-19
申请号:US18642987
申请日:2024-04-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Woo Seok Park , Jae Ho Jeon , Sung Gi Hur
Abstract: There is provided a semiconductor device capable of improving element performance and reliability. The semiconductor device may include an active pattern that includes a lower pattern extending in a first direction on a substrate and a sheet pattern on the lower pattern, a field insulating layer that defines the active pattern on the substrate, a gate structure on the lower pattern and including a gate insulating layer and a gate electrode, the gate electrode extending in a second direction perpendicular to the first direction, a gate spacer at least partially surrounding the gate structure and including a first portion on a sidewall of the gate structure and a second portion on a bottom surface of the gate structure, and a source/drain pattern on the lower pattern and in contact with the sheet pattern.
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公开(公告)号:US11908952B2
公开(公告)日:2024-02-20
申请号:US17840737
申请日:2022-06-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Woo Seok Park , Dong Chan Suh , Seung Min Song , Geum Jong Bae , Dong Il Bae
IPC: H01L29/786 , H01L29/423 , H01L29/10 , H01L29/161 , H01L29/08 , H01L29/66 , H01L29/775 , B82Y10/00 , H01L29/06
CPC classification number: H01L29/78696 , B82Y10/00 , H01L29/0673 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78618
Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.
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公开(公告)号:US11769813B2
公开(公告)日:2023-09-26
申请号:US18046518
申请日:2022-10-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Myung Gil Kang , Dong Won Kim , Woo Seok Park , Keun Hwi Cho , Sung Gi Hur
IPC: H01L29/423 , H01L27/092 , H01L29/06 , H01L29/786
CPC classification number: H01L29/42392 , H01L27/092 , H01L29/0665 , H01L29/4236 , H01L29/78696
Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.
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公开(公告)号:US11482606B2
公开(公告)日:2022-10-25
申请号:US17209290
申请日:2021-03-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Myung Gil Kang , Dong Won Kim , Woo Seok Park , Keun Hwi Cho , Sung Gi Hur
IPC: H01L29/423 , H01L27/092 , H01L29/786 , H01L29/06
Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.
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公开(公告)号:US20210091232A1
公开(公告)日:2021-03-25
申请号:US16953785
申请日:2020-11-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Woo Seok Park , Dong Chan Suh , Seung Min Song , Geum Jong Bae , Dong Il Bae
IPC: H01L29/786 , H01L29/423 , H01L29/10 , H01L29/161 , H01L29/08 , H01L29/66 , H01L29/775 , B82Y10/00 , H01L29/06
Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.
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