公开(公告)号：US20240085777A1

公开(公告)日：2024-03-14

申请号：US18326659

申请日：2023-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Young PARK ,  Jeong Hoon KO ,  Seong Ryeol KIM ,  Young-Gu KIM ,  Tae Hoon KIM ,  Hyun Joong KIM ,  Young Ju LEE

IPC: G03F1/36 ,  G03F1/80 ,  G03F1/84 ,  G03F7/00 ,  G03F7/20

CPC classification number: G03F1/36 ,  G03F1/80 ,  G03F1/84 ,  G03F7/70625 ,  G03F7/70683 ,  G03F7/706841

Abstract: Provided is a process proximity effect correction method capable of efficiently improving the dispersion of patterns. There is a process proximity effect correction method according to some embodiments, the process proximity effect correction method of a process proximity effect correction device for performing process proximity effect correction (PPC) of a plurality of patterns using a machine learning module executed by a processor, comprising: training a sensitivity model by inputting a layout image of the plurality of patterns and a layout critical dimension (CD) of the plurality of patterns into the machine learning module; estimating an after cleaning inspection critical dimension (ACI-CD) sensitivity prediction value of the plurality of patterns by inferring an ACI-CD prediction value of the plurality of patterns; and determining a correction rate of the layout CD of the plurality of patterns using the estimated sensitivity prediction value.

公开(公告)号：US20170213842A1

公开(公告)日：2017-07-27

申请号：US15067855

申请日：2016-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-chul PARK ,  Bio KIM ,  Young-Gu KIM ,  Jaehoon JEONG ,  Eunsuk CHO ,  Hyejin CHO ,  Jong In YUN

IPC: H01L27/115 ,  H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02238 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/40117

Abstract: A semiconductor memory device includes a substrate, a stack disposed on the substrate, a vertical channel structure penetrating the stack, and a fixed charge layer disposed in the vertical channel structure. The stack includes insulating patterns and gate electrodes alternately and repeatedly disposed on one another. The vertical channel structure includes a data storing pattern.