公开(公告)号：US20240069790A1

公开(公告)日：2024-02-29

申请号：US18137036

申请日：2023-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin AHN ,  Seoyeong Lee ,  Dongwoo Shin ,  Changjun Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: An operating method of a storage device including a memory controller and a non-volatile memory, the method including: performing a first read in response to a read request by reading data from the non-volatile memory using a default read voltage set; and performing a second read when the first read fails, by calculating a degradation compensation level, using a weight table, offset table, and displacement level, calculating a history read voltage set by performing an operation on the default read voltage set and degradation compensation level, and reading the data using the history read voltage set, wherein the weight table includes weights preset according to word line groups and state read voltages, the offset table includes offset levels preset according to the word line groups and the state read voltages, and the displacement level corresponds to a difference between a default read voltage level and an optimal read voltage level.

公开(公告)号：US20240153567A1

公开(公告)日：2024-05-09

申请号：US18209069

申请日：2023-06-13

Applicant: Samsung Electronics Co.,Ltd.

Inventor： Hyojin AHN ,  Seongkuk KIM ,  Dongwoo SHIN ,  Seoyeong LEE ,  Changjun LEE ,  Hoon JO

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/3409 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16

Abstract: The present disclosure provides apparatuses and methods for operating a flash memory for programming operating system (OS) data before an surface mount technology (SMT) process. In some embodiments, the method includes erasing a plurality of memory cells in a memory block, reducing a lateral charge loss of the plurality of memory cells due to high temperature degradation during the SMT process by applying a pre-program voltage to word lines coupled to the memory block, and performing multi-bit programming of the OS data in the plurality of memory cells, prior to performing the SMT process. The applying of the pre-program voltage causes threshold voltages of the plurality of memory cells to increase.

公开(公告)号：US20250068333A1

公开(公告)日：2025-02-27

申请号：US18945678

申请日：2024-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojin AHN ,  Seoyeong LEE ,  Hoon JO

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H10B43/27

Abstract: In some embodiments, an operating method of a storage device includes obtaining a plurality of points by searching for a first valley point between threshold voltage distributions of selection memory cells coupled to a selection word line of a plurality of word lines; calculating, using a first function, a first voltage level that corresponds to a first reference count value; calculating, using a second function, a second voltage level that corresponds to the first reference count value; classifying the selection memory cells into a plurality of coupling patterns according to an aggressor cell group of each of adjacent memory cells coupled to at least one adjacent word line adjacent to the selection word line; and performing a read operation, based on the plurality of coupling patterns of the selection memory cells, the first voltage level, and the second voltage level.

公开(公告)号：US20240152280A1

公开(公告)日：2024-05-09

申请号：US18220489

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin AHN ,  Dongwoo SHIN ,  Seongkuk KIM ,  Changjun LEE ,  Sungjun HONG

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F3/0647 ,  G06F3/0679 ,  G06F11/1008

Abstract: The present disclosure provides methods and apparatuses for programming operating system (OS) data before a surface mount technology (SMT) process. In some embodiments, a method includes erasing a plurality of memory cells in a memory block, classifying word lines coupled to the memory block into first word lines to be programmed with OS data and second word lines to be programmed in a state pattern, programming, with a multi-bit program, the OS data into first memory cells of the plurality of memory cells coupled to the first word lines, and programming second memory cells of the plurality of memory cells coupled to the second word lines to have the state pattern.