公开(公告)号：US20230078373A1

公开(公告)日：2023-03-16

申请号：US17989085

申请日：2022-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Jungho YOON ,  Youngjin CHO

IPC: H01L45/00 ,  H01L27/24

Abstract: A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer and a second layer. The first layer is formed of a first material. The second layer is on the first layer and formed of a second material having a density different from a density of the first material. The first conductive element and a second conductive element are located on the variable resistance layer and spaced apart from each other in order to form a current path in the variable resistance layer. The current path is in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

公开(公告)号：US20190037645A1

公开(公告)日：2019-01-31

申请号：US15868451

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Jinhong KIM ,  Haengdeog KOH ,  Doyoon KIM ,  Hajin KIM ,  Soichiro MIZUSAKI ,  Minjong BAE ,  Changsoo LEE

IPC: H05B3/14 ,  H05B3/26 ,  H01C17/06 ,  H01C17/30 ,  C03C3/064 ,  C03C4/16

CPC classification number: H05B3/141 ,  C03C3/064 ,  C03C4/16 ,  H01C17/06 ,  H01C17/30 ,  H05B3/262

Abstract: A The heating element structure includes: a conductive metal substrate; a heating layer spaced apart from the conductive metal substrate and configured to generate heat in response to an electrical signal; electrodes in contact with the heating layer and configured to provide the electrical signal to the heating layer; and a first insulating layer on the conductive metal substrate, the first insulating layer comprising a first matrix material and a particle, wherein a difference between a coefficient of thermal expansion (CTE) of the first matrix material and a coefficient of thermal expansion of the particle is about 4×10−6 per Kelvin or less.

公开(公告)号：US20180077755A1

公开(公告)日：2018-03-15

申请号：US15680830

申请日：2017-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seyun KIM ,  Haengdeog KOH ,  Doyoon KIM ,  Jinhong KIM ,  Hajin KIM ,  Soichiro MIZUSAKI ,  Minjong BAE ,  Hiesang SOHN ,  Changsoo LEE

IPC: H05B3/12 ,  H05B3/14 ,  H05B3/26

CPC classification number: H05B3/12 ,  H05B3/141 ,  H05B3/146 ,  H05B3/148 ,  H05B3/26 ,  H05B3/262 ,  H05B3/265 ,  H05B2203/013 ,  H05B2203/017 ,  H05B2214/04

Abstract: A heating element includes a matrix; and a plurality of conductive fillers, wherein some of the plurality of conductive fillers include first nano-sheets and first metal media configured to reduce a contact resistance between the first nano-sheets.

公开(公告)号：US20230337555A1

公开(公告)日：2023-10-19

申请号：US18338707

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Jungho YOON ,  Youngjin CHO

IPC: H01L47/00

CPC classification number: H10N70/231 ,  H10N70/8833 ,  H10B63/80

Abstract: A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer including a first material and a second layer on the first layer and the second layer including a second material. The second material has a different valence than a valence of the first material. The first conductive element and the second conductive element are on the variable resistance layer and separated from each other to form an electric current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

公开(公告)号：US20230086939A1

公开(公告)日：2023-03-23

申请号：US18058555

申请日：2022-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yumin KIM ,  Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Youngjin CHO

IPC: G11C16/26 ,  G11C16/30 ,  G11C5/06 ,  G11C16/14 ,  G11C16/04 ,  G11C16/24

Abstract: A nonvolatile memory device and an operating method thereof are provided. The nonvolatile memory device includes a memory cell array including first to third memory cells sequentially arranged in a vertical stack structure and a control logic configured to apply a first non-selection voltage to the first memory cell, apply a second non-selection voltage different from the first non-selection voltage to the third memory cell, apply a selection voltage to the second memory cell, and select the second memory cell as a selection memory cell.

公开(公告)号：US20210217473A1

公开(公告)日：2021-07-15

申请号：US17146999

申请日：2021-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjin CHO ,  Jungho YOON ,  Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI

IPC: G11C13/00 ,  G06N3/04 ,  H01L45/00 ,  H01L27/24

Abstract: A vertical nonvolatile memory device including a memory cell string using a resistance change material is disclosed. Each memory cell string of the nonvolatile memory device includes a semiconductor layer extending in a first direction and having a first surface opposite a second surface, a plurality of gates and a plurality of insulators alternately arranged in the first direction and extending in a second direction perpendicular to the first direction, a gate insulating layer extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer, and a dielectric film extending in the first direction on the surface of the semiconductor layer and having a plurality of movable oxygen vacancies distributed therein.

公开(公告)号：US20210193207A1

公开(公告)日：2021-06-24

申请号：US16876553

申请日：2020-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soichiro MIZUSAKI ,  Jungho YOON ,  Youngjin CHO

IPC: G11C11/22 ,  H01L29/51 ,  H01L29/78

Abstract: A nonvolatile memory cell resistance change type nonvolatile memory cell configured to store information by changing an electrical resistance according to application of electrical stress is provided and a nonvolatile memory device including the nonvolatile memory cell is provided. The resistance change type nonvolatile memory cell includes a resistance change material layer including a resistance change material; a ferroelectric layer on a first side of the resistance change material layer, the ferroelectric layer configured to change an electrical resistance of the resistance change material layer according to a polarization direction and polarization size of a ferroelectric therein; a first electrode on the ferroelectric layer and configured to control the polarization direction and the polarization size of the ferroelectric based on an applied voltage; and a second electrode and a third electrode on the resistance change material layer with the first electrode therebetween.

公开(公告)号：US20210035635A1

公开(公告)日：2021-02-04

申请号：US16802803

申请日：2020-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Jungho YOON ,  Cheolseong HWANG ,  Soichiro MIZUSAKI ,  Youngjin CHO

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.

公开(公告)号：US20240147868A1

公开(公告)日：2024-05-02

申请号：US18178103

申请日：2023-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soichiro MIZUSAKI ,  Kwangseok Kim ,  Jeongchun Ryu ,  Atsushi Okada

IPC: H10N50/10 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H01F10/3272 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: Disclosed are a spin orbit torque (SOT) magnetic memory device, an operating method thereof, and an electronic apparatus including the SOT magnetic memory device. The SOT magnetic memory device includes a first SOT layer, a magnetic tunnel junction (MTJ) layer on one surface of the first SOT layer, and an SOT-based local magnetic field generation layer to cross the first SOT layer and including a generating region configured to generate a magnetic field that reaches the MTJ layer; and an upper electrode layer disposed to face the first SOT layer with the MTJ layer therebetween and in contact with the MTJ layer. The SOT magnetic memory device includes five operating terminals.

公开(公告)号：US20210202833A1

公开(公告)日：2021-07-01

申请号：US16875119

申请日：2020-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Jungho YOON ,  Youngjin CHO

IPC: H01L45/00 ,  H01L27/24

Abstract: A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer including a first material and a second layer on the first layer and the second layer including a second material. The second material has a different valence than a valence of the first material. The first conductive element and the second conductive element are on the variable resistance layer and separated from each other to form an electric current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.