公开(公告)号：US20230386531A1

公开(公告)日：2023-11-30

申请号：US17828921

申请日：2022-05-31

Applicant: SanDisk Technologies LLC

Inventor： TIANYU TANG ,  Siddhesh Darne ,  Venkatesh Prasad Ramachandra

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1039 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/222

Abstract: A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second enable signals and utilizes rising or falling edges of a clock signal to latch the encoded bit information, which can then be decoded to determine corresponding command and address codes. A chip select sequence is also disclosed that enables a memory chip configuration to be employed in which each chip in a package shares a common connection to a controller but does not require hard-coded pins for performing chip select.

公开(公告)号：US20240071519A1

公开(公告)日：2024-02-29

申请号：US17898386

申请日：2022-08-29

Applicant: SanDisk Technologies LLC

Inventor： TIANYU TANG ,  Venkatesh Prasad Ramachandra ,  Siddhesh Darne

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

CPC classification number: G06F3/0613 ,  G06F3/0635 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

Abstract: The disclosure provides circuits and methods for increasing NAND input/output (I/O) bandwidth during read/write operations. The method includes transmitting a clock signal between a controller I/O circuit and a memory I/O circuit along a read enable bus, transmitting 8 bits of data along an I/O bus, and transmitting 2 bits of data along a data strobe signal (DQS) bus. Transmitting 2 bits of data along the DQS bus includes transmitting a first DQS data signal along the DQS bus and transmitting a first inverse DQS data signal along the DQS bus.

公开(公告)号：US12057189B2

公开(公告)日：2024-08-06

申请号：US17828921

申请日：2022-05-31

Applicant: SanDisk Technologies LLC

Inventor： Tianyu Tang ,  Siddhesh Darne ,  Venkatesh Prasad Ramachandra

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12

CPC classification number: G11C7/1039 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/222 ,  G11C8/10 ,  G11C8/12

Abstract: A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second enable signals and utilizes rising or falling edges of a clock signal to latch the encoded bit information, which can then be decoded to determine corresponding command and address codes. A chip select sequence is also disclosed that enables a memory chip configuration to be employed in which each chip in a package shares a common connection to a controller but does not require hard-coded pins for performing chip select.

公开(公告)号：US20240184667A1

公开(公告)日：2024-06-06

申请号：US18350350

申请日：2023-07-11

Applicant: SanDisk Technologies LLC

Inventor： SAJAL MITTAL ,  Siddhesh Darne

IPC: G06F11/10

CPC classification number: G06F11/1008

Abstract: A circuit for detecting an error in a byte of data transmitted over a channel includes a controller having a first DBI encoder configured to perform a first DBI encoding on a received byte of data. The circuit also includes a channel configured to receive the encoded byte from the controller. The circuit also includes a non-volatile memory having a second DBI encoder and configured to (1) perform a second DBI encoding on the encoded byte received over the channel, (2) check a DBI flag for the byte after the second DBI encoding, and (3) determine that the byte of data contains an error when the DBI flag after the second DBI encoding is 1. If the byte contains an error then it can be concluded that the channel contains a defect. In case of an error a write operation to memory core can be stopped.