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18 条记录 (耗时 0.023 秒)

    Adaptive phase-lead compensation with Miller Effect
    1.
    发明授权
    Adaptive phase-lead compensation with Miller Effect 有权
    采用米勒效应进行自适应相位补偿

    公开(公告)号：US09195249B2

    公开(公告)日：2015-11-24

    申请号：US13332142

    申请日：2011-12-20

    申请人： Sean S. Chen ,  Liwei Liu ,  Yongliang Wang

    发明人： Sean S. Chen ,  Liwei Liu ,  Yongliang Wang

    IPC分类号： G05F1/56 ,  G05F1/575

    CPC分类号： G05F1/575

    摘要： An adaptive phase-lead compensation (zero) circuit is disclosed that can be added to a circuit (e.g., a CMOS-based LDO) to ease the compensation and increase the phase margin of the circuit. By using the disclosed adaptive phase-lead compensation circuit, an adjustable resistance can be connected to any nodes in the compensated circuit rather than just to the voltage source (VDD) or ground (GND), allowing the Miller Effect to be used via a Miller capacitor.

    摘要翻译： 公开了可以添加到电路（例如，基于CMOS的LDO）的自适应相位超前补偿（零）电路，以便于补偿并增加电路的相位裕度。 通过使用所公开的自适应相位 - 引线补偿电路，可调电阻可以连接到补偿电路中的任何节点，而不仅仅是连接到电压源（VDD）或接地（GND），允许米勒效应通过米勒 电容器。

    ADAPTIVE PHASE-LEAD COMPENSATION WITH MILLER EFFECT
    2.
    发明申请
    ADAPTIVE PHASE-LEAD COMPENSATION WITH MILLER EFFECT 有权
    自适应相位补偿与米勒效应

    公开(公告)号：US20130154593A1

    公开(公告)日：2013-06-20

    申请号：US13332142

    申请日：2011-12-20

    申请人： Sean S. Chen ,  Liwei Liu ,  Yongliang Wang

    发明人： Sean S. Chen ,  Liwei Liu ,  Yongliang Wang

    IPC分类号： G05F1/10 ,  H03L5/00

    CPC分类号： G05F1/575

    摘要： An adaptive phase-lead compensation (zero) circuit is disclosed that can be added to a circuit (e.g., a CMOS-based LDO) to ease the compensation and increase the phase margin of the circuit. By using the disclosed adaptive phase-lead compensation circuit, an adjustable resistance can be connected to any nodes in the compensated circuit rather than just to the voltage source (VDD) or ground (GND), allowing the Miller Effect to be used via a Miller capacitor.

    摘要翻译： 公开了可以添加到电路（例如，基于CMOS的LDO）的自适应相位超前补偿（零）电路，以便于补偿并增加电路的相位裕度。 通过使用所公开的自适应相位 - 引线补偿电路，可调电阻可以连接到补偿电路中的任何节点，而不仅仅是连接到电压源（VDD）或接地（GND），允许米勒效应通过米勒 电容器。

    Voltage regulator with bypass mode
    3.
    发明申请
    Voltage regulator with bypass mode 有权
    电压调节器带旁路模式

    公开(公告)号：US20060164054A1

    公开(公告)日：2006-07-27

    申请号：US11042610

    申请日：2005-01-25

    申请人： Yongliang Wang ,  John Pasternak

    发明人： Yongliang Wang ,  John Pasternak

    IPC分类号： G05F1/40 ,  G05F1/618

    CPC分类号： G11C29/021 ,  G11C5/147 ,  G11C29/02 ,  G11C29/028

    摘要： A step down voltage regulator with bypass comprised of devices designed to operate over a maximum rated voltage lower than a supply voltage. The regulator includes an output regulation device coupled to the supply voltage and an output. An output device protection circuit is provided which is responsive to the supply voltage and the output to ensure that the maximum rated voltage of the output regulation device is not exceeded. A bypass circuit having a bypass output device and being coupled to the supply voltage is provided with a protection circuit. The output regulation devices comprise p-channel transistors, and may have an operating maximum rated voltage in a range of 2.7-3.6 volts with the supply voltage is in a range of 4.4-5.25 volts, or 2.9-3.5 volts.

    摘要翻译： 具有旁路的降压型稳压器包括设计成在低于电源电压的最大额定电压下工作的器件。 调节器包括耦合到电源电压和输出的输出调节器件。 提供输出装置保护电路，其响应于电源电压和输出，以确保不超过输出调节装置的最大额定电压。 具有旁路输出装置并且耦合到电源电压的旁路电路设置有保护电路。 输出调节装置包括p沟道晶体管，并且可以具有在2.7-3.6伏范围内的工作最大额定电压，而电源电压在4.4-5.25伏特或2.9-3.5伏特的范围内。

    Ultra-deep power-down mode for memory devices
    4.
    发明授权
    Ultra-deep power-down mode for memory devices 有权
    用于存储器件的超深度掉电模式

    公开(公告)号：US09037890B2

    公开(公告)日：2015-05-19

    申请号：US13559320

    申请日：2012-07-26

    申请人： Richard V De Caro ,  Danut Manea ,  Yongliang Wang ,  Stephen Trinh ,  Paul Hill

    发明人： Richard V De Caro ,  Danut Manea ,  Yongliang Wang ,  Stephen Trinh ,  Paul Hill

    IPC分类号： G06F1/26 ,  G06F1/32 ,  G11C5/14 ,  G11C16/30

    CPC分类号： G06F1/3296 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/147 ,  G11C5/148 ,  G11C16/30 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D50/20

    摘要： A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.

    摘要翻译： 存储器件包括电压调节器，其输出为存储器件的各种其他部件提供电压供应，包括命令用户界面。 存储器件通过向存储器件提供软件命令而被置于超深度掉电模式，该命令导致电压调节器的输出被禁止。 为了使存储器件脱离超深度掉电模式，芯片选择信号被提供给存储器件，其包括即使当存储器件处于超深度功率时仍保持通电的唤醒电路 降模式。 当存储器件处于超深度掉电模式时，芯片选择信号的接收使得电压调节器的输出被使能，从而为完全断电的部件提供电力。

    Self-configurable multi-regulator ASIC core power delivery
    6.
    发明授权
    Self-configurable multi-regulator ASIC core power delivery 有权
    自配置多调节器ASIC内核电源

    公开(公告)号：US07859134B2

    公开(公告)日：2010-12-28

    申请号：US12005056

    申请日：2007-12-21

    申请人： Steve X. Chi ,  Yongliang Wang ,  Ekram Hossain Bhuiyan ,  Daniel P. Nguyen ,  Vincent Anthony Condito ,  Po-Shen Lai

    发明人： Steve X. Chi ,  Yongliang Wang ,  Ekram Hossain Bhuiyan ,  Daniel P. Nguyen ,  Vincent Anthony Condito ,  Po-Shen Lai

    IPC分类号： H02J1/00 ,  H02J3/00

    CPC分类号： G06F1/26 ,  Y10T307/696

    摘要： A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

    摘要翻译： 一种用于操作具有专用半导体电路（ASIC）的电子产品的方法，该电子产品在其电路中包括与可选外部电容一起使用的线性调节器模块和耦合到产品的内部电容的无电容调节器模块，选择低功率子 模块或高功率子模块，用于ASIC的上电阶段。 ASIC的控制逻辑确定是否存在外部电容。 如果是这样，则在ASIC的上电阶段期间使用高功率无帽子模块; 如果不仅在ASIC的上电阶段期间使用低功率无帽子模块。 在ASIC上电之后，控制逻辑可以在某些操作时间内选择线性调节器模块，并在其他操作时间内选择无限幅调节器模块，或者可以在后期上电操作的所有时间中选择一个或另一个 。

    Self-configurable multi-regulator ASIC core power delivery
    7.
    发明申请
    Self-configurable multi-regulator ASIC core power delivery 审中-公开
    自配置多调节器ASIC内核电源

    公开(公告)号：US20090160423A1

    公开(公告)日：2009-06-25

    申请号：US12005126

    申请日：2007-12-21

    申请人： Steve X. Chi ,  Yongliang Wang ,  Ekram Hossain Bhuiyan ,  Daniel P. Nguyen ,  Vincent Anthony Condito ,  Po-Shen Lai

    发明人： Steve X. Chi ,  Yongliang Wang ,  Ekram Hossain Bhuiyan ,  Daniel P. Nguyen ,  Vincent Anthony Condito ,  Po-Shen Lai

    IPC分类号： G05B13/02

    CPC分类号： H03K19/0016

    摘要： An electronic product includes an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product. The capless regulator module includes both a low-power sub-module and a high-power sub-module. Control logic of the ASIC is configured to determine if an external capacitance is present. If so, the control logic causes the high-power capless regulator sub-module to be used during a power-up phase of the ASIC; if not, only the low-power capless regulator sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

    摘要翻译： 电子产品包括专用半导体电路（ASIC），其在其电路中包括与可选外部电容一起使用的线性调节器模块和耦合到产品的内部电容的无电容调节器模块。 无电容调节器模块包括低功率子模块和大功率子模块。 ASIC的控制逻辑被配置为确定是否存在外部电容。 如果是这样，则控制逻辑使得在ASIC的上电阶段期间使用大功率无电压调节器子模块; 如果不是，在ASIC的上电阶段只使用低功率无电压调节器子模块。 在ASIC上电之后，控制逻辑可以在某些操作时间内选择线性调节器模块，并在其他操作时间内选择无限幅调节器模块，或者可以在后期上电操作的所有时间中选择一个或另一个 。

    Voltage regulator with bypass mode
    9.
    发明授权
    Voltage regulator with bypass mode 有权
    电压调节器带旁路模式

    公开(公告)号：US07391193B2

    公开(公告)日：2008-06-24

    申请号：US11042610

    申请日：2005-01-25

    申请人： Yongliang Wang ,  John Pasternak

    发明人： Yongliang Wang ,  John Pasternak

    IPC分类号： G05F1/40 ,  G05F1/10 ,  H02H3/20

    CPC分类号： G11C29/021 ,  G11C5/147 ,  G11C29/02 ,  G11C29/028

    摘要： A step down voltage regulator with bypass comprised of devices designed to operate over a maximum rated voltage lower than a supply voltage. The regulator includes an output regulation device coupled to the supply voltage and an output. An output device protection circuit is provided which is responsive to the supply voltage and the output to ensure that the maximum rated voltage of the output regulation device is not exceeded. A bypass circuit having a bypass output device and being coupled to the supply voltage is provided with a protection circuit. The output regulation devices comprise p-channel transistors, and may have an operating maximum rated voltage in a range of 2.7-3.6 volts with the supply voltage is in a range of 4.4-5.25 volts, or 2.9-3.5 volts.

    摘要翻译： 具有旁路的降压型稳压器包括设计成在低于电源电压的最大额定电压下工作的器件。 调节器包括耦合到电源电压和输出的输出调节器件。 提供输出装置保护电路，其响应于电源电压和输出，以确保不超过输出调节装置的最大额定电压。 具有旁路输出装置并且耦合到电源电压的旁路电路设置有保护电路。 输出调节装置包括p沟道晶体管，并且可以具有在2.7-3.6伏范围内的工作最大额定电压，而电源电压在4.4-5.25伏特或2.9-3.5伏特的范围内。

    Voltage regulator using protected low voltage devices
    10.
    发明申请
    Voltage regulator using protected low voltage devices 有权
    稳压器采用受保护的低压器件

    公开(公告)号：US20050179421A1

    公开(公告)日：2005-08-18

    申请号：US10814518

    申请日：2004-03-31

    申请人： Yongliang Wang ,  John Pasternak

    发明人： Yongliang Wang ,  John Pasternak

    IPC分类号： G05F1/40 ,  G05F1/565 ,  G06F1/26 ,  G11C5/14

    CPC分类号： G06F1/266 ,  G05F1/565 ,  G11C5/147

    摘要： A step down voltage regulator including devices designed to operate over a maximum rated voltage lower than the supply voltage. The regulator comprises an output regulation device coupled to the supply voltage and an output; and an output device protection circuit responsive to the supply voltage and the output to ensure that the maximum rated voltage of the output device is not exceeded. Also provided is a method for operating a voltage regulator in a memory system. The method includes the steps of: providing a voltage regulator having an input and an output, and including a plurality of devices operating at a maximum rated voltage less than the voltage provided at the input; and controlling the gate voltage of the output device responsive to a load on the regulator output, so that the maximum rated voltage is not exceeded.

    摘要翻译： 降压型稳压器包括设计为在低于电源电压的最大额定电压下工作的器件。 调节器包括耦合到电源电压和输出的输出调节器件; 以及响应于电源电压和输出的输出装置保护电路，以确保不超过输出装置的最大额定电压。 还提供了一种用于操作存储器系统中的稳压器的方法。 该方法包括以下步骤：提供具有输入和输出的电压调节器，并且包括以低于输入端提供的电压的最大额定电压工作的多个器件; 以及响应于调节器输出上的负载来控制输出装置的栅极电压，使得不超过最大额定电压。