公开(公告)号：US20140284668A1

公开(公告)日：2014-09-25

申请号：US14296854

申请日：2014-06-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuya TSURUME

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L27/1214 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1266 ,  H01L27/13 ,  H01L2221/68359 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2924/01025 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An object of the present invention is to provide a semiconductor device having a conductive film, which sufficiently serves as an antenna, and a method for manufacturing thereof. The semiconductor device has an element formation layer including a transistor, which is provided over a substrate, an insulating film provided on the element formation layer, and a conductive film serving as an antenna, which is provided on the insulating film. The insulating film has a groove. The conductive film is provided along the surface of the insulating film and the groove. The groove of the insulating film may be provided to pass through the insulating film. Alternatively, a concave portion may be provided in the insulating film so as not to pass through the insulating film. A structure of the groove is not particularly limited, and for example, the groove can be provided to have a tapered shape, etc.

Abstract translation: 本发明的目的是提供一种具有充分用作天线的导电膜的半导体器件及其制造方法。 半导体器件具有包括设置在衬底上的晶体管，设置在元件形成层上的绝缘膜和用作天线的导电膜的元件形成层，其设置在绝缘膜上。 绝缘膜具有凹槽。 导电膜沿着绝缘膜和槽的表面设置。 可以提供绝缘膜的沟槽以通过绝缘膜。 或者，可以在绝缘膜中设置凹部以不通过绝缘膜。 槽的结构没有特别限制，例如可以将槽设置成具有锥形等。

公开(公告)号：US20130323912A1

公开(公告)日：2013-12-05

申请号：US13950957

申请日：2013-07-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoko TAMURA ,  Eiji SUGIYAMA ,  Yoshitaka DOZEN ,  Koji DAIRIKI ,  Takuya TSURUME

IPC: H01L21/02

CPC classification number: H01L21/02381 ,  H01L21/84 ,  H01L27/1214 ,  H01L27/1266 ,  H01L27/13 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/81001

Abstract: A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.

Abstract translation: 形成在衬底上的释放层; 在剥离层上形成薄膜集成电路中的至少一个; 在薄膜集成电路中的至少一个上形成膜; 并通过使用蚀刻剂除去释放层; 因此，薄膜集成电路中的至少一个从基板剥离。 半导体器件通过层压等密封剥离的薄膜集成电路而形成。

公开(公告)号：US20160233340A1

公开(公告)日：2016-08-11

申请号：US15017831

申请日：2016-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Akihisa SHIMOMURA ,  Satoru OKAMOTO ,  Yutaka OKAZAKI ,  Yoshinobu ASAMI ,  Hiroaki HONDA ,  Takuya TSURUME

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L21/385 ,  H01L27/1225 ,  H01L29/0688 ,  H01L29/42384 ,  H01L29/78696

Abstract: A transistor with favorable electrical characteristics is provided. A transistor with stable electrical characteristics is provided. A semiconductor device having a high degree of integration is provided. Side surfaces of an oxide semiconductor layer in which a channel is formed are covered with an oxide semiconductor layer, whereby impurity diffusion from the side surfaces of the oxide semiconductor into the inside can be prevented. A gate electrode is formed by a damascene process, whereby transistors can be miniaturized and formed at a high density.

Abstract translation: 提供具有良好电特性的晶体管。 提供具有稳定电特性的晶体管。 提供了具有高集成度的半导体器件。 其中沟道形成的氧化物半导体层的侧表面被氧化物半导体层覆盖，从而可以防止从氧化物半导体的侧表面向内部的杂质扩散。 栅电极通过镶嵌工艺形成，由此可以以高密度小型化和形成晶体管。

公开(公告)号：US20140220745A1

公开(公告)日：2014-08-07

申请号：US14217519

申请日：2014-03-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Ryosuke WATANABE ,  Hidekazu TAKAHASHI ,  Takuya TSURUME

IPC: H01L21/56

CPC classification number: H01L21/56 ,  B32B37/20 ,  B32B2305/342 ,  B42D25/45 ,  B42D2033/46 ,  G06K19/07718 ,  G06K19/07749 ,  G06K19/0775 ,  H01L21/67126 ,  H01L21/67132 ,  H01L21/67144 ,  H01L21/6835 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68318 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2924/0002 ,  Y10T156/1089 ,  Y10T156/1093 ,  Y10T156/1712 ,  H01L2924/00

Abstract: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.

Abstract translation: 本发明的目的是提高密封薄膜集成电路的生产效率并防止损坏和断裂。 此外，本发明的另一个目的是防止薄膜集成电路在运输中受损，并且使得更容易处理薄膜集成电路。 本发明提供了一种层压系统，其中辊子用于供应用于密封的基板，接收IC芯片，分离和密封。 通过旋转辊可以连续地进行多个薄膜集成电路的分离，密封和接收; 从而可以极大地提高生产效率。 此外，由于使用了彼此相对的一对辊，所以能够容易地密封薄膜集成电路。

公开(公告)号：US20150255489A1

公开(公告)日：2015-09-10

申请号：US14718701

申请日：2015-05-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuya TSURUME ,  Yoshitaka DOZEN

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L21/304 ,  H01L21/76898 ,  H01L27/1218 ,  H01L27/1266 ,  H01L27/13 ,  H01L29/78 ,  H01L29/78603 ,  H01L2924/0002 ,  H01L2924/00

Abstract: It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface. A means for thinning the substrate can be performed by partially removing the substrate by performing grinding treatment, polishing treatment, etching by chemical treatment, or the like from the back surface of the substrate.

Abstract translation: 本发明的目的是提供一种半导体器件，其中即使在堆叠设置在衬底上的多个半导体元件的情况下，堆叠的半导体元件也可以通过衬底电连接及其制造方法。 根据本发明的一个特征，一种制造半导体器件的方法包括以下步骤：在衬底的上表面中选择性地形成凹陷或形成通过背面穿透上表面的开口; 形成具有晶体管以覆盖基板的上表面和凹陷或开口的元件组; 以及通过使基板从后表面变薄而暴露出形成在凹陷或开口中的元件组。 可以通过从基板的背面进行研磨处理，研磨处理，化学处理等的蚀刻等部分去除基板来进行薄板化的方法。

公开(公告)号：US20140368230A1

公开(公告)日：2014-12-18

申请号：US14471801

申请日：2014-08-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuya TSURUME ,  Etsuko ASANO

IPC: G01R31/26

CPC classification number: G01R31/2601 ,  G01R31/2607 ,  G01R31/2822 ,  G01R31/2884 ,  H01L21/6835 ,  H01L21/78 ,  H01L22/14 ,  H01L22/34 ,  H01L23/66 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To provide a semiconductor device capable of being easily subjected to a physical test without deteriorating characteristics. According to a measuring method of a semiconductor device in which an element layer provided with a test element including a terminal portion is sealed with first and second films having flexibility, the first film formed over the terminal portion is removed to form a contact hole reaching the terminal portion; the contact hole is filled with a resin containing a conductive material; heating is carried out after arranging a wiring substrate having flexibility over the resin with which filling has been performed so that the terminal portion and the wiring substrate having flexibility are electrically connected via the resin containing a conductive material; and a measurement is performed.

Abstract translation: 提供能够容易进行物理测试而不劣化特性的半导体器件。 根据半导体器件的测量方法，其中设置有包括端子部分的测试元件的元件层被具有柔性的第一和第二膜密封，去除在端子部分上形成的第一膜以形成到达 端子部分 接触孔填充含有导电材料的树脂; 在将具有柔性的布线基板布置在已经进行了填充的树脂上之后进行加热，使得具有柔性的端子部分和布线基板通过包含导电材料的树脂电连接; 并进行测量。

公开(公告)号：US20140027762A1

公开(公告)日：2014-01-30

申请号：US13942866

申请日：2013-07-16

Applicant: Semiconductor Energy Laboratory Co. Ltd.

Inventor： Takuya TSURUME ,  Hideomi Suzawa

IPC: H01L29/24

CPC classification number: H01L29/24 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device is provided, which includes a first oxide semiconductor layer over a substrate, a second oxide semiconductor layer over and in contact the first oxide semiconductor layer, a source electrode and a drain electrode over the second oxide semiconductor layer, a gate insulating layer over the second oxide semiconductor layer, and a gate electrode over the gate insulating layer. The first oxide semiconductor layer has a step portion. The step portion is thinner than a portion other than the step portion. A surface of the step portion is in contact with the source electrode and the drain electrode.

Abstract translation: 提供一种半导体器件，其包括在衬底上的第一氧化物半导体层，在第一氧化物半导体层上方并与其接触的第二氧化物半导体层，在第二氧化物半导体层上的源电极和漏电极，栅极绝缘层 在第二氧化物半导体层上方，以及在栅极绝缘层上方的栅电极。 第一氧化物半导体层具有台阶部。 台阶部比台阶部以外的部分薄。 台阶部分的表面与源电极和漏电极接触。

公开(公告)号：US20170084630A1

公开(公告)日：2017-03-23

申请号：US15255602

申请日：2016-09-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuya TSURUME ,  Yoshitaka DOZEN

IPC: H01L27/12 ,  H01L21/768

CPC classification number: H01L27/124 ,  H01L21/304 ,  H01L21/76898 ,  H01L27/1218 ,  H01L27/1266 ,  H01L27/13 ,  H01L29/78 ,  H01L29/78603 ,  H01L2924/0002 ,  H01L2924/00

Abstract: It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface. A means for thinning the substrate can be performed by partially removing the substrate by performing grinding treatment, polishing treatment, etching by chemical treatment, or the like from the back surface of the substrate.

公开(公告)号：US20150179696A1

公开(公告)日：2015-06-25

申请号：US14636996

申请日：2015-03-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA ,  Takuya TSURUME

IPC: H01L27/146 ,  G01T1/208 ,  G01T1/20

CPC classification number: H01L27/14643 ,  G01T1/2018 ,  G01T1/208 ,  H01L27/144 ,  H01L27/14601 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14678 ,  H04N5/357 ,  H04N5/3745

Abstract: To provide a photodetector circuit capable of obtaining signals in different periods without being affected by characteristics of a photoelectric conversion element. The photodetector circuit has n signal output circuits (n is a natural number of 2 or more) connected to the photoelectric conversion element. Further, the n signal output circuits each include the following: a transistor whose gate potential varies in accordance with the amount of light entering the photoelectric conversion element; a first switching element which holds the gate potential of the transistor; and a second switching element which controls a signal output from the transistor. Thus, after data based on the amount of light entering the photoelectric conversion elements is held as the gate potentials of the transistors, the second switching elements are turned on, whereby signals in different periods can be obtained without being affected by characteristics of the photoelectric conversion element.

Abstract translation: 提供能够在不受光电转换元件的特性影响的情况下在不同时期获得信号的光检测器电路。 光电检测器电路具有连接到光电转换元件的n个信号输出电路（n为2以上的自然数）。 此外，n个信号输出电路各自包括以下：栅极电位根据进入光电转换元件的光量而变化的晶体管; 保持晶体管的栅极电位的第一开关元件; 以及控制从晶体管输出的信号的第二开关元件。 因此，在基于进入光电转换元件的光量的数据被保持为晶体管的栅极电位之后，第二开关元件导通，从而可以获得不同周期的信号而不受光电转换的特性的影响 元件。

公开(公告)号：US20140038373A1

公开(公告)日：2014-02-06

申请号：US14050634

申请日：2013-10-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuya TSURUME ,  Yoshitaka DOZEN

IPC: H01L21/304 ,  H01L29/78

CPC classification number: H01L27/124 ,  H01L21/304 ,  H01L21/76898 ,  H01L27/1218 ,  H01L27/1266 ,  H01L27/13 ,  H01L29/78 ,  H01L29/78603 ,  H01L2924/0002 ,  H01L2924/00

Abstract: It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface. A means for thinning the substrate can be performed by partially removing the substrate by performing grinding treatment, polishing treatment, etching by chemical treatment, or the like from the back surface of the substrate.

Abstract translation: 本发明的目的是提供一种半导体器件，其中即使在堆叠设置在衬底上的多个半导体元件的情况下，堆叠的半导体元件也可以通过衬底电连接及其制造方法。 根据本发明的一个特征，一种制造半导体器件的方法包括以下步骤：在衬底的上表面中选择性地形成凹陷或形成通过背面穿透上表面的开口; 形成具有晶体管以覆盖基板的上表面和凹陷或开口的元件组; 以及通过使基板从后表面变薄而暴露出形成在凹陷或开口中的元件组。 可以通过从基板的背面进行研磨处理，研磨处理，化学处理等的蚀刻等部分去除基板来进行薄板化的方法。