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    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20100155799A1

    公开(公告)日：2010-06-24

    申请号：US12638066

    申请日：2009-12-15

    申请人： Shigeyuki YOKOYAMA

    发明人： Shigeyuki YOKOYAMA

    IPC分类号： H01L27/108 ,  H01L27/088 ,  H01L21/8242

    CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

    摘要： A first MOS transistor includes, as a first impurity region, a pair of first source/drain regions including first portions formed in a semiconductor substrate and second portions formed so as to project upward from the first portions. A second MOS transistor includes a pair of second source/drain regions including second impurity regions formed in the semiconductor substrate, third impurity regions located in contact with the second impurity regions so as to project upward from the semiconductor substrate, and fourth impurity regions located on the third impurity regions. The concentration of impurities in the third impurity regions is lower than that of impurities in the fourth impurity regions. The concentration of impurities in the first impurity regions is lower than that of impurities in the second impurity regions. The first, the second, the third and the fourth impurity regions are same conductivity type.

    摘要翻译： 第一MOS晶体管包括作为第一杂质区域的一对第一源极/漏极区域，包括形成在半导体衬底中的第一部分和形成为从第一部分向上突出的第二部分。 第二MOS晶体管包括一对第二源/漏区，包括形成在半导体衬底中的第二杂质区，与第二杂质区接触的第三杂质区，以便从半导体衬底向上突出，第四杂质区位于 第三杂质区。 第三杂质区域中的杂质浓度低于第四杂质区域中的杂质浓度。 第一杂质区域中的杂质浓度低于第二杂质区域中的杂质浓度。 第一，第二，第三和第四杂质区域具有相同的导电类型。

    METHODS OF PREPARING SAMPLES FOR MALDI MASS SPECTROMETRY AND REAGENT COMPOSITIONS FOR THE SAME
    5.
    发明申请
    METHODS OF PREPARING SAMPLES FOR MALDI MASS SPECTROMETRY AND REAGENT COMPOSITIONS FOR THE SAME 失效
    制备用于MALDI质谱的样品和其试剂组合物的方法

    公开(公告)号：US20080067343A1

    公开(公告)日：2008-03-20

    申请号：US11772799

    申请日：2007-07-02

    申请人： Hiroshi HIROTA ,  Miwako ASANUMA ,  Seketsu FUKUZAWA ,  Shigeyuki YOKOYAMA

    发明人： Hiroshi HIROTA ,  Miwako ASANUMA ,  Seketsu FUKUZAWA ,  Shigeyuki YOKOYAMA

    IPC分类号： B01D59/44

    CPC分类号： G01N33/6851 ,  H01J49/0418

    摘要： A simple and efficient method of preparing a sample in the measurement according to matrix-assisted laser desorption/ionization mass spectrometry (MALDI-MS) capable of inhibiting any ion suppression by impurities, such as inorganic salts and surfactants, contained in the sample. An analyte and matrix molecules are co-crystallized in the presence of porous microparticles. Preferably, this co-crystallization is carried out by bringing the analyte, matrix molecules and porous microparticles into contact with each other on a target plate and thereafter drying the mixture. The porous microparticles consist of an ion exchanger having an average particle diameter of not more than 50 μm, preferably a strongly basic anion exchanger.

    摘要翻译： 根据能够抑制样品中所含杂质如无机盐和表面活性剂的任何离子抑制的基质辅助激光解吸/电离质谱法（MALDI-MS），在测量中制备样品的简单有效的方法。 分析物和基质分子在多孔微粒存在下共结晶。 优选地，通过使分析物，基质分子和多孔微粒在靶板上彼此接触，然后干燥混合物来进行共结晶。 多孔微粒由平均粒径不大于50μm，优选强碱性阴离子交换剂的离子交换剂组成。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开

    公开(公告)号：US20080150030A1

    公开(公告)日：2008-06-26

    申请号：US11959070

    申请日：2007-12-18

    申请人： Shigeyuki YOKOYAMA ,  Yu Kosuge

    发明人： Shigeyuki YOKOYAMA ,  Yu Kosuge

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： A semiconductor device includes a double gate transistor which comprises an active region of a fin type and a pair of gate electrodes disposed opposite to each other through the active region. A height of the gate electrodes is higher than that of the active region and equal to or smaller than a calculated gate electrode height calculated using the following formula: ( ( Gate   Electrode   Height  [ nm ] ) - ( Active   Region   Height  [ nm ] ) ) / ( Active   Region   Height  [ nm ] ) = 3.5    - 5 × ( Gate   Length  [ nm ] ) 2 - 0.002 × ( Gate   Length  [ nm ] ) + 0.16 .