公开(公告)号：US08735889B2

公开(公告)日：2014-05-27

申请号：US13286280

申请日：2011-11-01

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L29/04

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

摘要翻译： 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1μm以上。

公开(公告)号：US20120043580A1

公开(公告)日：2012-02-23

申请号：US13286280

申请日：2011-11-01

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L33/62 ,  H01L21/336 ,  H01L29/772

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

摘要翻译： 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1μm以上。

公开(公告)号：US06984550B2

公开(公告)日：2006-01-10

申请号：US10718584

申请日：2003-11-24

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/8244

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

公开(公告)号：US06657260B2

公开(公告)日：2003-12-02

申请号：US10078489

申请日：2002-02-21

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L2701

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 &mgr;m or more.

摘要翻译： 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1um以上。

公开(公告)号：US08053339B2

公开(公告)日：2011-11-08

申请号：US12124385

申请日：2008-05-21

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L21/20

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

摘要翻译： 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1μm以上。

公开(公告)号：US20050092996A1

公开(公告)日：2005-05-05

申请号：US10978512

申请日：2004-11-02

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L29/786 ,  G02F1/1362 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

摘要翻译： 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1um以上。

公开(公告)号：US07405115B2

公开(公告)日：2008-07-29

申请号：US10978512

申请日：2004-11-02

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L21/00

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

摘要翻译： 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1um以上。

公开(公告)号：US20090035922A1

公开(公告)日：2009-02-05

申请号：US12124385

申请日：2008-05-21

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L21/20

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

摘要翻译： 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1um以上。

公开(公告)号：US20070013859A1

公开(公告)日：2007-01-18

申请号：US11525016

申请日：2006-09-22

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

IPC分类号： C30B33/00 ,  G02F1/1339

CPC分类号： H01L29/4908 ,  G02F2001/13629 ,  H01L23/5283 ,  H01L23/53223 ,  H01L27/3241 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648 ,  H01L51/5203 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  H01L2924/00

摘要： The wiring of the present invention has a layered structure that includes a first conductive layer (first layer) having a first width and made of one or a plurality of kinds of elements selected from W and Mo, or an alloy or compound mainly containing the element, a low-resistant second conductive layer (second layer) having a second width smaller than the first width, and made of an alloy or a compound mainly containing Al, and a third conductive layer (third layer) having a third width smaller than the second width, and made of an alloy or compound mainly containing Ti. With this constitution, the present invention is fully ready for enlargement of a pixel portion. At least edges of the second conductive layer have a taper-shaped cross-section. Because of this shape, satisfactory coverage can be obtained.

公开(公告)号：US08207536B2

公开(公告)日：2012-06-26

申请号：US13104140

申请日：2011-05-10

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

IPC分类号： H01L31/00

CPC分类号： H01L27/1296 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863

摘要： For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

摘要翻译： 为了形成栅电极，层叠具有低电阻的包含Al或以Al为主要成分的材料的导电膜和用于防止Al扩散到半导体层中的具有低接触电阻的导电膜，并且栅电极由 使用能够高速进行蚀刻处理的装置。