公开(公告)号：US08735889B2

公开(公告)日：2014-05-27

申请号：US13286280

申请日：2011-11-01

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L29/04

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

摘要翻译： 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1μm以上。

公开(公告)号：US08461596B2

公开(公告)日：2013-06-11

申请号：US13288300

申请日：2011-11-03

申请人： Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Shunpei Yamazaki

发明人： Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Shunpei Yamazaki

IPC分类号： H01L27/14 ,  H01L21/00

CPC分类号： H01L29/78621 ,  G02F1/1368 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1288 ,  H01L29/06 ,  H01L29/66765 ,  H01L29/78669

摘要： The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask.

摘要翻译： 本发明的目的是提供一种实现生产率和产量提高的有源矩阵液晶显示装置。 在本发明中，使用相同的蚀刻气体选择性地蚀刻包括含有金属材料的导电膜和含有一种导电类型的杂质元素的第二非晶半导体膜和非晶半导体膜的层叠膜，以形成第一 非晶半导体膜1001成锥形。 由此，可以解决像素电极1003的覆盖问题，并且可以用三个光掩模来完成反交错型TFT。

公开(公告)号：US20120043580A1

公开(公告)日：2012-02-23

申请号：US13286280

申请日：2011-11-01

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L33/62 ,  H01L21/336 ,  H01L29/772

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

摘要翻译： 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1μm以上。

公开(公告)号：US20100200855A1

公开(公告)日：2010-08-12

申请号：US12766172

申请日：2010-04-23

申请人： Hideomi SUZAWA ,  Yoshihiro KUSUYAMA ,  Shunpei YAMAZAKI

发明人： Hideomi SUZAWA ,  Yoshihiro KUSUYAMA ,  Shunpei YAMAZAKI

IPC分类号： H01L29/04

CPC分类号： H01L29/78621 ,  G02F1/1368 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1288 ,  H01L29/06 ,  H01L29/66765 ,  H01L29/78669

摘要： The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type can be completed with three photomask.

摘要翻译： 本发明的目的是提供一种实现生产率和产量提高的有源矩阵液晶显示装置。 在本发明中，使用相同的蚀刻气体选择性地蚀刻包括含有金属材料的导电膜和含有一种导电类型的杂质元素的第二非晶半导体膜和非晶半导体膜的层叠膜，以形成第一 非晶半导体膜1001成锥形。 由此，可以解决像素电极1003的覆盖问题，并且可以用三个光掩模来完成反交错类型。

公开(公告)号：US20100155732A1

公开(公告)日：2010-06-24

申请号：US12637317

申请日：2009-12-14

申请人： Hideomi Suzawa ,  Yoshihiro Kusuyama

发明人： Hideomi Suzawa ,  Yoshihiro Kusuyama

IPC分类号： H01L33/00 ,  H01L29/786

CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/76801 ,  H01L21/76804 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.

摘要翻译： 本发明的目的是提供一种半导体器件的制造方法，其中由于通过在不同材料和膜厚度的层压膜（无机绝缘膜和有机树脂膜）中同时形成接触孔而减少了工艺数量（无机绝缘膜和有机树脂膜） 进行一次蚀刻。 通过将干蚀刻（有机树脂膜503的蚀刻速率/含有氮的无机绝缘膜502的蚀刻速度）的选择比设定为1.6〜2.9，优选为1.9，即使在 不同材料和膜厚度的膜可以在两个接触孔中几乎相同。

公开(公告)号：US20070013859A1

公开(公告)日：2007-01-18

申请号：US11525016

申请日：2006-09-22

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

IPC分类号： C30B33/00 ,  G02F1/1339

CPC分类号： H01L29/4908 ,  G02F2001/13629 ,  H01L23/5283 ,  H01L23/53223 ,  H01L27/3241 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648 ,  H01L51/5203 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  H01L2924/00

摘要： The wiring of the present invention has a layered structure that includes a first conductive layer (first layer) having a first width and made of one or a plurality of kinds of elements selected from W and Mo, or an alloy or compound mainly containing the element, a low-resistant second conductive layer (second layer) having a second width smaller than the first width, and made of an alloy or a compound mainly containing Al, and a third conductive layer (third layer) having a third width smaller than the second width, and made of an alloy or compound mainly containing Ti. With this constitution, the present invention is fully ready for enlargement of a pixel portion. At least edges of the second conductive layer have a taper-shaped cross-section. Because of this shape, satisfactory coverage can be obtained.

公开(公告)号：US06984550B2

公开(公告)日：2006-01-10

申请号：US10718584

申请日：2003-11-24

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/8244

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

公开(公告)号：US06686228B2

公开(公告)日：2004-02-03

申请号：US10189935

申请日：2002-07-03

申请人： Hideomi Suzawa ,  Yoshihiro Kusuyama

发明人： Hideomi Suzawa ,  Yoshihiro Kusuyama

IPC分类号： H01L2100

CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/76801 ,  H01L21/76804 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.

公开(公告)号：US06475836B1

公开(公告)日：2002-11-05

申请号：US09535835

申请日：2000-03-28

申请人： Hideomi Suzawa ,  Yoshihiro Kusuyama

发明人： Hideomi Suzawa ,  Yoshihiro Kusuyama

IPC分类号： H01L2100

CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/76801 ,  H01L21/76804 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.

公开(公告)号：US20120264245A1

公开(公告)日：2012-10-18

申请号：US13531149

申请日：2012-06-22

申请人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Koji ONO ,  Yoshihiro KUSUYAMA

发明人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Koji ONO ,  Yoshihiro KUSUYAMA

IPC分类号： H01L33/08

CPC分类号： H01L27/1296 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863

摘要： For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

摘要翻译： 为了形成栅电极，层叠具有低电阻的包含Al或以Al为主要成分的材料的导电膜和用于防止Al扩散到半导体层中的具有低接触电阻的导电膜，并且栅电极由 使用能够高速进行蚀刻处理的装置。