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    Clock Circuit And Method For Recalibrating An Injection Oscillator Coupled To Kick-Start A Crystal Oscillator
    1.
    发明申请
    Clock Circuit And Method For Recalibrating An Injection Oscillator Coupled To Kick-Start A Crystal Oscillator 审中-公开

    公开(公告)号：US20200099337A1

    公开(公告)日：2020-03-26

    申请号：US16136739

    申请日：2018-09-20

    Applicant: Silicon Laboratories Inc.

    Inventor： Matthew Powell ,  Sudipta Sarkar

    IPC: H03B5/06 ,  H03B5/36 ,  H03K21/38 ,  H03L3/00

    Abstract: Embodiments of clock circuits disclosed herein include a crystal oscillator circuit, an injection oscillator coupled to kick-start the crystal oscillator circuit and a digital frequency calibration circuit coupled to recalibrate the injection oscillator. The crystal oscillator circuit is configured to generate a clock signal at a resonant frequency. The injection oscillator is coupled to supply an oscillation signal at an injection frequency to the crystal oscillator circuit to reduce a start-up time of the crystal oscillator circuit. The digital frequency calibration circuit is coupled to receive the resonant frequency and the injection frequency as inputs, and configured to supply a digital control signal to the injection oscillator to set the injection frequency of the injection oscillator substantially equal to the resonant frequency of the crystal oscillator circuit. Methods are provided herein to recalibrate the injection frequency of an injection oscillator over time, temperature and/or supply voltage.

    Slew-rate controlled supply voltage switching
    2.
    发明授权
    Slew-rate controlled supply voltage switching 有权

    公开(公告)号：US10468983B2

    公开(公告)日：2019-11-05

    申请号：US14933285

    申请日：2015-11-05

    Applicant: SILICON LABORATORIES INC.

    Inventor： Mohamed Mostafa Elsayed ,  Kenneth W. Fernald ,  Matthew Powell

    IPC: H02M3/158 ,  H03K17/04 ,  H02M1/00

    Abstract: An apparatus includes a slew rate regulation circuit, a plurality of switches and a controller circuit. The controller circuit controls the plurality of switches to decouple a first source supply voltage from a supply rail; control the plurality of switches to couple a second source supply voltage to the supply rail to replace the first source supply voltage with the second source supply voltage; and control the slew rate regulation circuit to regulate a slew rate of a voltage of the supply rail during a time interval in which the first source supply voltage is being replaced with the second source supply voltage.

    Clock circuit and method for recalibrating an injection oscillator coupled to kick-start a crystal oscillator
    5.
    发明授权
    Clock circuit and method for recalibrating an injection oscillator coupled to kick-start a crystal oscillator 审中-公开

    公开(公告)号：US10673383B2

    公开(公告)日：2020-06-02

    申请号：US16136739

    申请日：2018-09-20

    Applicant: Silicon Laboratories Inc.

    Inventor： Matthew Powell ,  Sudipta Sarkar

    IPC: H03B5/06 ,  H03B5/36 ,  H03L3/00 ,  H03K21/38

    Abstract: Embodiments of clock circuits disclosed herein include a crystal oscillator circuit, an injection oscillator coupled to kick-start the crystal oscillator circuit and a digital frequency calibration circuit coupled to recalibrate the injection oscillator. The crystal oscillator circuit is configured to generate a clock signal at a resonant frequency. The injection oscillator is coupled to supply an oscillation signal at an injection frequency to the crystal oscillator circuit to reduce a start-up time of the crystal oscillator circuit. The digital frequency calibration circuit is coupled to receive the resonant frequency and the injection frequency as inputs, and configured to supply a digital control signal to the injection oscillator to set the injection frequency of the injection oscillator substantially equal to the resonant frequency of the crystal oscillator circuit. Methods are provided herein to recalibrate the injection frequency of an injection oscillator over time, temperature and/or supply voltage.

    Digital signal transfer between multiple voltage domains
    6.
    发明授权
    Digital signal transfer between multiple voltage domains 有权

    公开(公告)号：US10355477B2

    公开(公告)日：2019-07-16

    申请号：US14927810

    申请日：2015-10-30

    Applicant: Silicon Laboratories Inc.

    Inventor： Mohamed Elsayed ,  Matthew Powell ,  Nicholas M. Atkinson ,  Praveen Kallam

    IPC: H02J1/10 ,  G06F1/26 ,  H03K19/0185 ,  G06F1/28 ,  G06F1/30 ,  H02J1/00

    Abstract: Circuitry and methods are provided that may be implemented to transfer digital signals between multiple voltage domains while some of these domains may be invalid, e.g., such as to transfer a digital signal from a source voltage domain to a destination voltage domain while the voltage of the source domain is zero or invalid. Possible implementations include, but are not limited to, for power selection and distribution in an integrated circuit chip that has multiple power sources (e.g., such as main power supply and a backup power supply), and in which at startup the chip is agnostic of (or is not aware of) which power supply or power supplies is actually powered and available.

    OVER VOLTAGE TOLERANT CIRCUIT
    7.
    发明申请
    OVER VOLTAGE TOLERANT CIRCUIT 审中-公开

    公开(公告)号：US20170093388A1

    公开(公告)日：2017-03-30

    申请号：US14871734

    申请日：2015-09-30

    Applicant: Silicon Laboratories Inc.

    Inventor： CHAO YANG ,  Matthew Powell

    IPC: H03K17/082

    CPC classification number: H03K19/0185

    Abstract: An apparatus includes an integrated circuit, which includes a processor core, a plurality of input/output (I/O) circuits, and a plurality of over voltage tolerant (OVT) circuits. Each I/O circuit is associated with an I/O pad and is associated with an OVT circuit of the plurality of OVT circuits. At least one of the OVT circuits includes a passive circuit, which is adapted to receive a pad voltage from the associated I/O pad; receive a supply voltage of the associated I/O circuit; and based on a relationship of the received pad voltage relative to the received supply voltage, selectively couple a gate of a transistor of the associated I/O circuit to the pad voltage to inhibit a leakage current.

    Over voltage tolerant circuit
    8.
    发明授权
    Over voltage tolerant circuit 有权

    公开(公告)号：US10090838B2

    公开(公告)日：2018-10-02

    申请号：US14871734

    申请日：2015-09-30

    Applicant: Silicon Laboratories Inc.

    Inventor： Chao Yang ,  Matthew Powell

    IPC: H03K19/0185

    Abstract: An apparatus includes an integrated circuit, which includes a processor core, a plurality of input/output (I/O) circuits, and a plurality of over voltage tolerant (OVT) circuits. Each I/O circuit is associated with an I/O pad and is associated with an OVT circuit of the plurality of OVT circuits. At least one of the OVT circuits includes a passive circuit, which is adapted to receive a pad voltage from the associated I/O pad; receive a supply voltage of the associated I/O circuit; and based on a relationship of the received pad voltage relative to the received supply voltage, selectively couple a gate of a transistor of the associated I/O circuit to the pad voltage to inhibit a leakage current.

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