公开(公告)号：US09564238B1

公开(公告)日：2017-02-07

申请号：US14919005

申请日：2015-10-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Ning Bai ,  Hieu Van Tran ,  Qing Rao ,  Parviz Ghazavi ,  Kai Man Yue

IPC: G11C16/28 ,  G11C16/14

CPC classification number: G11C16/28 ,  G11C7/14 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30 ,  G11C2216/04

Abstract: The present invention relates to a flash memory device that uses dummy memory cells as source line pull down circuits. In one embodiment, when a memory cell is in read mode or erase mode, its source line is coupled to ground through a bitline of a dummy memory cell, which in turn is coupled to ground. When the memory cell is in program mode, the bitline of the dummy memory cell is coupled to an inhibit voltage, which places the dummy memory cell in a program inhibit mode that maintains the dummy memory cell in erased state.

Abstract translation: 本发明涉及使用虚拟存储单元作为源极线下拉电路的闪速存储器件。 在一个实施例中，当存储器单元处于读取模式或擦除模式时，其源极线通过虚拟存储器单元的位线耦合到地，而虚拟存储器单元进一步耦合到地。 当存储器单元处于编程模式时，虚拟存储单元的位线被耦合到禁止电压，这使得虚拟存储单元处于将虚拟存储单元维持为擦除状态的程序禁止模式。

公开(公告)号：US20170194055A1

公开(公告)日：2017-07-06

申请号：US15371496

申请日：2016-12-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Xiao Yan Pi ,  Kai Man Yue ,  Qing Rao ,  Lisa Bian

IPC: G11C16/26 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28 ,  G11C16/32 ,  G11C2207/2254

Abstract: Multiple embodiments of a low power sense amplifier for use in a flash memory system are disclosed. In some embodiments, the loading on a sense amplifier can be adjusted by selectively attaching one or more bit lines to the sense amplifier, where the one or more bit lines each is coupled to an extraneous memory cell.

公开(公告)号：US10199109B2

公开(公告)日：2019-02-05

申请号：US15371496

申请日：2016-12-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Xiao Yan Pi ,  Kai Man Yue ,  Qing Rao ,  Lisa Bian

IPC: G11C16/28 ,  G11C16/26 ,  G11C16/24 ,  G11C7/06 ,  G11C7/14 ,  G11C16/04 ,  G11C16/32

Abstract: Multiple embodiments of a low power sense amplifier for use in a flash memory system are disclosed. In some embodiments, the loading on a sense amplifier can be adjusted by selectively attaching one or more bit lines to the sense amplifier, where the one or more bit lines each is coupled to an extraneous memory cell.