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    Array Of Non-volatile Memory Cells With ROM Cells
    1.
    发明申请
    Array Of Non-volatile Memory Cells With ROM Cells 有权
    具有ROM单元的非易失性存储单元阵列

    公开(公告)号：US20160254269A1

    公开(公告)日：2016-09-01

    申请号：US14639063

    申请日：2015-03-04

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

    IPC: H01L27/115 ,  H01L29/788 ,  H01L29/423

    CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

    Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

    Abstract translation: 一种存储器件，其包括多个ROM单元，每个ROM单元具有形成在衬底中的间隔开的源极和漏极区域，其间具有沟道区域，设置在沟道区域的第一部分上方并与沟道区域的第一部分绝缘的第一栅极， 与沟道区的第二部分绝缘，以及在多个ROM单元上延伸的导电线。 导电线电耦合到ROM单元的第一子组的漏极区域，并且不电耦合到ROM单元的第二子组的漏极区域。 或者，ROM单元的第一子组各自包括沟道区域中的较高电压阈值注入区域，而ROM单元的第二子组每个在沟道区域中都缺少任何较高电压阈值注入区域。

    Flash memory system using memory cell as source line pull down circuit
    9.
    发明授权
    Flash memory system using memory cell as source line pull down circuit 有权
    闪存系统使用存储单元作为源极线下拉电路

    公开(公告)号：US09564238B1

    公开(公告)日：2017-02-07

    申请号：US14919005

    申请日：2015-10-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Ning Bai ,  Hieu Van Tran ,  Qing Rao ,  Parviz Ghazavi ,  Kai Man Yue

    IPC: G11C16/28 ,  G11C16/14

    CPC classification number: G11C16/28 ,  G11C7/14 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30 ,  G11C2216/04

    Abstract: The present invention relates to a flash memory device that uses dummy memory cells as source line pull down circuits. In one embodiment, when a memory cell is in read mode or erase mode, its source line is coupled to ground through a bitline of a dummy memory cell, which in turn is coupled to ground. When the memory cell is in program mode, the bitline of the dummy memory cell is coupled to an inhibit voltage, which places the dummy memory cell in a program inhibit mode that maintains the dummy memory cell in erased state.

    Abstract translation: 本发明涉及使用虚拟存储单元作为源极线下拉电路的闪速存储器件。 在一个实施例中，当存储器单元处于读取模式或擦除模式时，其源极线通过虚拟存储器单元的位线耦合到地，而虚拟存储器单元进一步耦合到地。 当存储器单元处于编程模式时，虚拟存储单元的位线被耦合到禁止电压，这使得虚拟存储单元处于将虚拟存储单元维持为擦除状态的程序禁止模式。

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