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    WEAR LEVELING IN EEPROM EMULATOR FORMED OF FLASH MEMORY CELLS
    2.
    发明申请
    WEAR LEVELING IN EEPROM EMULATOR FORMED OF FLASH MEMORY CELLS 有权

    公开(公告)号：US20210264996A1

    公开(公告)日：2021-08-26

    申请号：US17006550

    申请日：2020-08-28

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Guangming Lin ,  Xiaozhou Qian ,  Xiao Yan Pi ,  Vipin Tiwari ,  Zhenlin Ding

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

    Abstract: The present invention relates to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. Each bit in each index word is associated with a physical address for a physical word in the emulated EEPROM, and the index word keeps track of which physical word is the current word for a particular logical address. The use of the index word enables a wear leveling algorithm that allows for a programming command to a logical address to result in: (i) skipping the programming operation if the data stored in the current word does not contain a “1” that corresponds to a “0” in the data to be stored, (ii) reprogramming one or more bits of the current word in certain situations, or (iii) shifting to and programming the next physical word in certain situations.

    Non-volatile memory device with stored index information
    5.
    发明授权
    Non-volatile memory device with stored index information 有权

    公开(公告)号：US11074980B2

    公开(公告)日：2021-07-27

    申请号：US16813317

    申请日：2020-03-09

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Xiaozhou Qian ,  Xiao Yan Pi ,  Vipin Tiwari

    IPC: G11C16/14 ,  G11C7/10 ,  G11C16/28

    Abstract: A memory device that includes a memory array having pluralities of non-volatile memory cells, a plurality of index memory cells each associated with a different one of the pluralities of the non-volatile memory cells, and a controller. The controller is configured to erase the pluralities of non-volatile memory cells, set each of the index memory cells to a first state, and program first data into the memory array by reading the plurality of index memory cells and determining that a first one of the index memory cells is in the first state, programming the first data into the plurality of the non-volatile memory cells associated with the first one of the index memory cells, and setting the first one of the index memory cells to a second state different from the first state.

    Wear leveling in EEPROM emulator formed of flash memory cells
    8.
    发明授权
    Wear leveling in EEPROM emulator formed of flash memory cells 有权

    公开(公告)号：US11626176B2

    公开(公告)日：2023-04-11

    申请号：US17571443

    申请日：2022-01-07

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Guangming Lin ,  Xiaozhou Qian ,  Xiao Yan Pi ,  Vipin Tiwari ,  Zhenlin Ding

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G06F12/02

    Abstract: The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. The embodiments comprise a system and method for receiving an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in an array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word; when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and when the current word is not the last physical word in the sector, changing a next index bit.

    Wear leveling in EEPROM emulator formed of flash memory cells
    9.
    发明授权
    Wear leveling in EEPROM emulator formed of flash memory cells 有权

    公开(公告)号：US11257555B2

    公开(公告)日：2022-02-22

    申请号：US17006550

    申请日：2020-08-28

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Guangming Lin ,  Xiaozhou Qian ,  Xiao Yan Pi ,  Vipin Tiwari ,  Zhenlin Ding

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/14 ,  G11C16/10 ,  G06F12/02 ,  G06F12/08

    Abstract: The present invention relates to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. Each bit in each index word is associated with a physical address for a physical word in the emulated EEPROM, and the index word keeps track of which physical word is the current word for a particular logical address. The use of the index word enables a wear leveling algorithm that allows for a programming command to a logical address to result in: (i) skipping the programming operation if the data stored in the current word does not contain a “1” that corresponds to a “0” in the data to be stored, (ii) reprogramming one or more bits of the current word in certain situations, or (iii) shifting to and programming the next physical word in certain situations.

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