公开(公告)号：US20170207104A1

公开(公告)日：2017-07-20

申请号：US15478508

申请日：2017-04-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

公开(公告)号：US20180138158A1

公开(公告)日：2018-05-17

申请号：US15867910

申请日：2018-01-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Hao Tung ,  Chang-Yi Lan ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Shu-Huei Huang

IPC: H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.

公开(公告)号：US20150041972A1

公开(公告)日：2015-02-12

申请号：US14249626

申请日：2014-04-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Kai Shih ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chu-Chi Hsu ,  Shih-Hao Tung

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L24/97 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor package is disclosed, which includes: a first substrate; a first semiconductor component disposed on the first substrate; a second substrate disposed on the first semiconductor component and electrically connected to the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate and encapsulating the first semiconductor component and the conductive elements. The present invention can control the height and volume of the conductive elements since the distance between the first substrate and the second substrate is fixed by bonding the second substrate to the first semiconductor component.

Abstract translation: 公开了一种半导体封装，其包括：第一衬底; 设置在所述第一基板上的第一半导体部件; 第二基板，设置在所述第一半导体部件上，并且通过多个导电元件电连接到所述第一基板; 以及形成在第一基板和第二基板之间并封装第一半导体部件和导电元件的第一密封剂。 本发明可以控制导电元件的高度和体积，因为通过将第二基板结合到第一半导体部件来固定第一基板和第二基板之间的距离。

公开(公告)号：US09905546B2

公开(公告)日：2018-02-27

申请号：US14211244

申请日：2014-03-14

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Shih-Hao Tung ,  Chang-Yi Lan ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chu-Huei Huang

IPC: H01L21/56 ,  H01L23/28 ,  H01L25/00 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.

公开(公告)号：US09646921B2

公开(公告)日：2017-05-09

申请号：US14255326

申请日：2014-04-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

公开(公告)号：US10163662B2

公开(公告)日：2018-12-25

申请号：US15478508

申请日：2017-04-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

公开(公告)号：US20150187741A1

公开(公告)日：2015-07-02

申请号：US14211244

申请日：2014-03-14

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Shih-Hao Tung ,  Chang-Yi Lan ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chu-Huei Huang

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.

Abstract translation: 提供了一种用于制造封装（PoP）封装结构的方法，其包括：提供具有至少第一电子元件和多个第一支撑部分的第一封装基板，其中第一电子元件电连接到第一封装 基质; 在所述第一包装基板上形成密封剂，以密封所述第一电子元件和所述第一支撑部分; 在所述密封剂中形成多个开口以暴露所述第一支撑部分的表面的部分; 以及提供具有多个第二支撑部分的第二包装基板，并且将第二包装基板堆叠在第一包装基板上，其中第二支撑部分位于密封剂的开口中并与第一支撑部分结合。 因此，密封剂有效地将第一支撑部分或第二支撑部分彼此分离，以防止在它们之间发生桥接。

公开(公告)号：US20150187722A1

公开(公告)日：2015-07-02

申请号：US14255326

申请日：2014-04-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

Abstract translation: 提供一种半导体封装，其包括：具有相对的第一和第二表面的封装基板和形成在第一表面上的多个第一和第二导电焊盘; 具有相反的有源和无源表面的芯片，并经由其主动表面设置在第一导电焊盘上; 分别形成在所述第二导电焊盘上的多个导电柱; 以及形成在所述封装基板的所述第一表面上的第一密封剂，用于封装所述芯片和所述导电柱，并且具有用于暴露所述导电柱的上表面的多个开口，从而增加所述封装密度并保护所述芯片和所述互连结构 受到水分侵入的不利影响。