公开(公告)号：US10763237B2

公开(公告)日：2020-09-01

申请号：US16691477

申请日：2019-11-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Min Lo ,  Chee-Key Chung ,  Chang-Fu Lin ,  Kuo-Hua Yu ,  Hsiang-Hua Huang

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/00

Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.

公开(公告)号：US20230136541A1

公开(公告)日：2023-05-04

申请号：US17568913

申请日：2022-01-05

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： You-Chen Lin ,  Yu-Min Lo ,  Kuo-Hua Yu ,  Jun-Hao Feng

IPC: H01L23/538 ,  H01L21/48

Abstract: An electronic package is provided and includes a protection layer formed on the electronic structure having a plurality of conductors to cover the plurality of conductors, a dielectric layer having a plurality of grooves to enable the electronic structure to be bonded onto one side of the dielectric layer with the protection layer thereon such that each of the plurality of conductors is correspondingly accommodated in each of the plurality of grooves, and a plurality of conductive components disposed on another side of the dielectric layer. Accordingly, the design of the grooves is used to correspond to the high and low surfaces of the electronic structure such that the problem of poor manufacturing process can be avoided.

公开(公告)号：US10522500B2

公开(公告)日：2019-12-31

申请号：US15980255

申请日：2018-05-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Min Lo ,  Chee-Key Chung ,  Chang-Fu Lin ,  Kuo-Hua Yu ,  Hsiang-Hua Huang

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/00

Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.

公开(公告)号：US20190252344A1

公开(公告)日：2019-08-15

申请号：US15980255

申请日：2018-05-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Min Lo ,  Chee-Key Chung ,  Chang-Fu Lin ,  Kuo-Hua Yu ,  Hsiang-Hua Huang

IPC: H01L23/00 ,  H01L21/48

Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.

公开(公告)号：US20180269142A1

公开(公告)日：2018-09-20

申请号：US15590111

申请日：2017-05-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chee-Key Chung ,  Yu-Min Lo ,  Han-Hung Chen ,  Chang-Fu Lin ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L23/14 ,  H01L23/28

CPC classification number: H01L23/49827 ,  H01L23/147 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012

Abstract: The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.

公开(公告)号：US12132003B2

公开(公告)日：2024-10-29

申请号：US17568913

申请日：2022-01-05

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： You-Chen Lin ,  Yu-Min Lo ,  Kuo-Hua Yu ,  Jun-Hao Feng

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5381 ,  H01L23/481 ,  H01L25/0655

Abstract: An electronic package is provided and includes a protection layer formed on the electronic structure having a plurality of conductors to cover the plurality of conductors, a dielectric layer having a plurality of grooves to enable the electronic structure to be bonded onto one side of the dielectric layer with the protection layer thereon such that each of the plurality of conductors is correspondingly accommodated in each of the plurality of grooves, and a plurality of conductive components disposed on another side of the dielectric layer. Accordingly, the design of the grooves is used to correspond to the high and low surfaces of the electronic structure such that the problem of poor manufacturing process can be avoided.

公开(公告)号：US20230223316A1

公开(公告)日：2023-07-13

申请号：US17956566

申请日：2022-09-29

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Tai-Shin Renn ,  Kuo-Hua Yu ,  Yu-Min Lo ,  Wei-Shen Hung

IPC: H01L23/367 ,  H01L23/00 ,  H01L21/48 ,  H01L25/10 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/3677 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L21/4853 ,  H01L25/105 ,  H01L21/568 ,  H01L21/4882 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49833 ,  H01L2924/3511 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: An electronic package is provided, in which an electronic element is disposed on an upper side of a circuit structure, a package layer covers the electronic element, and an action structure is embedded in the package layer, so that the action structure is exposed from a surface of the package layer, and then a bonding element is disposed on a lower side of the circuit structure and corresponding to the position of the action structure, so as to form a thermal conduction between the bonding element and the action structure. Therefore, a laser can transfer heat energy to the bonding element via the action structure, so that a solder material on the bonding element can be reflowed.

公开(公告)号：US20200091109A1

公开(公告)日：2020-03-19

申请号：US16691477

申请日：2019-11-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Min Lo ,  Chee-Key Chung ,  Chang-Fu Lin ,  Kuo-Hua Yu ,  Hsiang-Hua Huang

IPC: H01L23/00 ,  H01L21/48

Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.

公开(公告)号：US10361150B2

公开(公告)日：2019-07-23

申请号：US15590111

申请日：2017-05-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chee-Key Chung ,  Yu-Min Lo ,  Han-Hung Chen ,  Chang-Fu Lin ,  Fu-Tang Huang

IPC: H01L23/14 ,  H01L23/28 ,  H01L23/31 ,  H01L23/498

Abstract: The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.