公开(公告)号：US5635747A

公开(公告)日：1997-06-03

申请号：US481098

申请日：1995-06-07

申请人： Hyong-Gon Lee ,  Sang-Ki Hwang ,  Cheol-Ung Jang ,  Young-Wi Ko ,  Sung-Hee Cho

发明人： Hyong-Gon Lee ,  Sang-Ki Hwang ,  Cheol-Ung Jang ,  Young-Wi Ko ,  Sung-Hee Cho

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C17/12 ,  H01L21/8247 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/115 ,  G11C17/123 ,  H01L27/112

摘要： A nonvolatile semiconductor memory with a unit cell structure suitable for high speed operation and a low power supply voltage. The nonvolatile semiconductor memory includes a switching circuit including block select transistors connected by its respective terminal to a corresponding bit line. This switching circuit transmits a signal only when a string to which the switching circuit corresponds is selected. A second active region having a different impurity concentration from a first active region constituting source and drain regions of memory transistors is formed at a substrate contact portion of a bit line contact portion where the memory string and bit line are connected. The impurity concentration of the second active region is lower than that of the first active region.

摘要翻译： 具有适用于高速运行和低电源电压的单元结构的非易失性半导体存储器。 非易失性半导体存储器包括切换电路，其包括通过其相应端子连接到相应位线的块选择晶体管。 该切换电路仅在选择与开关电路对应的串时发送信号。 在构成存储晶体管的源区和漏区的第一有源区具有不同杂质浓度的第二有源区形成在连接存储器串和位线的位线接触部的衬底接触部分。 第二有源区的杂质浓度低于第一有源区的杂质浓度。

公开(公告)号：US07218371B2

公开(公告)日：2007-05-15

申请号：US11166010

申请日：2005-06-24

申请人： Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

发明人： Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

IPC分类号： G02F1/1345 ,  G02F1/1343

CPC分类号： G02F1/133512 ,  G02F1/134336 ,  G02F1/1345 ,  G02F2001/133337 ,  G02F2001/133388 ,  G02F2001/133397 ,  G09G3/3648 ,  G09G2330/08 ,  G09G2330/10

摘要： In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.

摘要翻译： 在液晶显示器中，多个栅极线和数据线设置在包括显示区域作为屏幕的第一基板上，以及在显示区域外部的外围区域，其中多个像素电极电连接到栅极线 和数据线，并且一些像素电极延伸到位于周边区域中; 并且可选地，在与第一基板相对设置的第二基板上形成黑矩阵，用于屏蔽位于周边区域中的像素电极的延伸部分，在第一和第二基板上形成定向膜的摩擦方向朝向 位于周边区域中的像素电极的延伸部分，使得取向膜表面上的杂质离子沿着摩擦方向行进，以在像素电极的延伸部分处停止，并且筛选由杂质离子引起的图像缺陷区域 与黑色矩阵。

公开(公告)号：US5528537A

公开(公告)日：1996-06-18

申请号：US505038

申请日：1995-07-21

申请人： Hyong-Gon Lee ,  Sang-Ki Hwang ,  Cheol-Ung Jang ,  Young-Wi Ko ,  Sung-Hee Cho

发明人： Hyong-Gon Lee ,  Sang-Ki Hwang ,  Cheol-Ung Jang ,  Young-Wi Ko ,  Sung-Hee Cho

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C17/12 ,  H01L21/8247 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/115 ,  G11C17/123 ,  H01L27/112

摘要： A nonvolatile semiconductor memory with a unit cell structure suitable for high speed operation and a low power supply voltage. The nonvolatile semiconductor memory includes a switching circuit including block select transistors connected by its respective terminal to a corresponding bit line. This switching circuit transmits a signal only when a string to which the switching circuit corresponds is selected. A second active region having a different impurity concentration from a first active region constituting source and drain regions of memory transistors is formed at a substrate contact portion of a bit line contact portion where the memory string and bit line are connected. The impurity concentration of the second active region is lower than that of the first active region.

摘要翻译： 具有适用于高速运行和低电源电压的单元结构的非易失性半导体存储器。 非易失性半导体存储器包括切换电路，其包括通过其相应端子连接到相应位线的块选择晶体管。 该切换电路仅在选择与开关电路对应的串时发送信号。 在构成存储晶体管的源区和漏区的第一有源区具有不同杂质浓度的第二有源区形成在连接存储器串和位线的位线接触部的衬底接触部分。 第二有源区的杂质浓度低于第一有源区的杂质浓度。

公开(公告)号：US5469450A

公开(公告)日：1995-11-21

申请号：US099331

申请日：1993-07-30

申请人： Sung-Hee Cho ,  Hyong-Gon Lee

发明人： Sung-Hee Cho ,  Hyong-Gon Lee

IPC分类号： G11C17/00 ,  G06F11/10 ,  G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C29/42

CPC分类号： G06F11/1008 ,  G06F11/1076

摘要： A nonvolatile memory device containing sub memory arrays and distinct associated peripheral sub array circuits containing error checking and correction circuits that are similarly positioned according to the sub array. The memory device is configured so that a single mask change allows the device to be manufactured as a normal mode device or a page mode device.

摘要翻译： 一种包含副存储器阵列和不同的相关联的外围子阵列电路的非易失性存储器件，其包含根据子阵列类似地定位的错误检查和校正电路。 存储器件被配置为使得单个掩模改变允许将器件制造为普通模式器件或页模式器件。

公开(公告)号：US5357530A

公开(公告)日：1994-10-18

申请号：US934249

申请日：1992-08-25

申请人： Hyong-Gon Lee ,  Sung-Hee Cho

发明人： Hyong-Gon Lee ,  Sung-Hee Cho

IPC分类号： G11C11/409 ,  G06F11/10 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/22

摘要： A data output control circuit of a semiconductor memory device. The data output control circuit comprises an input signal detector for detecting a desired signal, a controller for selecting one of a plurality of data output buffers and a data output controller for driving the selected data output buffer. A signal for driving and controlling the data output buffer is enabled after the data of a given memory cell is supplied to an input terminal of the data output buffer so that any unnecessary transition operation of data can be eliminated to reduce the current dissipation of a semiconductor memory chip and to prevent the deterioration of data access time for the purpose of improving the yield of the semiconductor memory chip.

摘要翻译： 半导体存储器件的数据输出控制电路。 数据输出控制电路包括用于检测所需信号的输入信号检测器，用于选择多个数据输出缓冲器中的一个的控制器和用于驱动所选数据输出缓冲器的数据输出控制器。 在给定存储单元的数据被提供给数据输出缓冲器的输入端之后，启用用于驱动和控制数据输出缓冲器的信号，从而可以消除数据的任何不必要的转换操作以减少半导体的电流耗散 以防止数据存取时间的恶化，以提高半导体存储芯片的产量。

公开(公告)号：US20070229747A1

公开(公告)日：2007-10-04

申请号：US11743378

申请日：2007-05-02

申请人： Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

发明人： Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

IPC分类号： G02F1/1343

CPC分类号： G02F1/133512 ,  G02F1/134336 ,  G02F1/1345 ,  G02F2001/133337 ,  G02F2001/133388 ,  G02F2001/133397 ,  G09G3/3648 ,  G09G2330/08 ,  G09G2330/10

摘要： In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrode, and an image defect area caused by the impurity ions is screened with the black matrix.

摘要翻译： 在液晶显示器中，多个栅极线和数据线设置在包括显示区域作为屏幕的第一基板上，以及在显示区域外部的外围区域，其中多个像素电极电连接到栅极线 和数据线，并且一些像素电极延伸到位于周边区域中; 并且可选地，在与第一基板相对设置的第二基板上形成黑矩阵，用于屏蔽位于周边区域中的像素电极的延伸部分，在第一和第二基板上形成定向膜的摩擦方向朝向 位于外围区域的像素电极的延伸部分，使得取向膜表面上的杂质离子沿着摩擦方向行进，以在像素电极的延伸部分停止，并且屏蔽由杂质离子引起的图像缺陷区域 与黑色矩阵。

公开(公告)号：US5313425A

公开(公告)日：1994-05-17

申请号：US051408

申请日：1993-04-23

申请人： Hyong-Gon Lee ,  Sung-Hee Cho ,  Se-Jin Kim

发明人： Hyong-Gon Lee ,  Sung-Hee Cho ,  Se-Jin Kim

IPC分类号： G06F11/16 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G11C13/00

CPC分类号： G11C29/88 ,  G06F11/1008

摘要： A semiconductor memory device which is comprised of a plurality m of electrically isolated data memory sub-arrays for storing data bits and a plurality k of electrically isolated parity memory sub-arrays for storing parity bits, wherein each of the data and parity memory sub-arrays includes a plurality of memory cells arranged in a matrix of rows and columns, with the memory cells in each row connected to a common word line and the memory cells in each column connected to a common bit line. Row address decoders function to activate a selected word line in each of the memory sub-arrays, and column address decoders, in combination with column selection circuitry, function to couple a selected bit line in each of the memory sub-arrays to a plurality m of sense amplifiers, which function to sense the voltage level of respective ones of the selected bit lines, and produce output data and parity bits representative of these sensed voltage levels. An error checking and correction circuit compares the output data and parity bits in order to detect and correct errors in the output data bits. Because of the unique architecture of the semiconductor memory device of this invention, defects in word lines or bit lines are confined to a single bit, thereby rendering these defects easily reparable by means of an ECC circuit alone, and thus dispensing with the need for a redundant memory circuit.

摘要翻译： 一种半导体存储器件，包括用于存储数据位的多个电绝缘数据存储器子阵列和用于存储奇偶校验位的多个电隔离奇偶校验存储器子阵列，其中数据和奇偶校验存储器子阵列中的每一个， 阵列包括以行和列的矩阵排列的多个存储单元，每行中的存储单元连接到公共字线，并且每列中的存储单元连接到公共位线。 行地址解码器用于激活每个存储器子阵列中的所选择的字线以及与列选择电路组合的列地址解码器，用于将每个存储器子阵列中的选定位线耦合到多个m 感测放大器，其用于感测所选位线中的相应位线的电压电平，并且产生表示这些感测电压电平的输出数据和奇偶校验位。 错误检查和校正电路比较输出数据和奇偶校验位，以便检测和纠正输出数据位中的错误。 由于本发明的半导体存储器件的独特架构，字线或位线中的缺陷被限制在单个位，从而使得这些缺陷易于通过ECC电路单独进行修复，从而不需要一个 冗余存储电路。

公开(公告)号：US20050237466A1

公开(公告)日：2005-10-27

申请号：US11166010

申请日：2005-06-24

申请人： Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

发明人： Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

IPC分类号： G02F1/1337 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1362

CPC分类号： G02F1/133512 ,  G02F1/134336 ,  G02F1/1345 ,  G02F2001/133337 ,  G02F2001/133388 ,  G02F2001/133397 ,  G09G3/3648 ,  G09G2330/08 ,  G09G2330/10

摘要： In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.

公开(公告)号：US06927830B2

公开(公告)日：2005-08-09

申请号：US10178016

申请日：2002-06-20

申请人： Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

发明人： Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

IPC分类号： G02F1/1337 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1362 ,  G09G3/30 ,  G09G3/36

CPC分类号： G02F1/133512 ,  G02F1/134336 ,  G02F1/1345 ,  G02F2001/133337 ,  G02F2001/133388 ,  G02F2001/133397 ,  G09G3/3648 ,  G09G2330/08 ,  G09G2330/10

摘要： In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.

摘要翻译： 在液晶显示器中，多个栅极线和数据线设置在包括显示区域作为屏幕的第一基板上，以及在显示区域外部的外围区域，其中多个像素电极电连接到栅极线 和数据线，并且一些像素电极延伸到位于周边区域中; 并且可选地，在与第一基板相对设置的第二基板上形成黑矩阵，用于屏蔽位于周边区域中的像素电极的延伸部分，在第一和第二基板上形成定向膜的摩擦方向朝向 位于周边区域中的像素电极的延伸部分，使得取向膜表面上的杂质离子沿着摩擦方向行进，以在像素电极的延伸部分处停止，并且筛选由杂质离子引起的图像缺陷区域 与黑色矩阵。

公开(公告)号：US5736772A

公开(公告)日：1998-04-07

申请号：US633450

申请日：1996-04-17

申请人： Young-Wi Ko ,  Yun-Jin Cho ,  Sung-Hee Cho ,  Hyong-Gon Lee

发明人： Young-Wi Ko ,  Yun-Jin Cho ,  Sung-Hee Cho ,  Hyong-Gon Lee

IPC分类号： H01L21/28 ,  H01L27/02 ,  H01L27/06 ,  H01L27/108 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L27/0629 ,  H01L27/0251

摘要： A polysilicon gate electrode of an integrated circuit field effect transistor is formed in two portions which are isolated from one another. The first portion is formed on the gate insulating region. The second portion is formed on the semiconductor substrate outside the gate insulating region and is electrically insulated from the first portion. Since the first and second portions of the polysilicon gate electrode are isolated from one another, only the charge which is on the first polysilicon portion contributes to gate insulating region degradation during plasma etching. After polysilicon gate electrode formation, the first and second portions may be electrically connected by a link. Field effect transistor performance and/or reliability are thereby increased.

摘要翻译： 集成电路场效应晶体管的多晶硅栅电极形成为彼此隔离的两部分。 第一部分形成在栅绝缘区上。 第二部分形成在栅极绝缘区域外部的半导体衬底上，并与第一部分电绝缘。 由于多晶硅栅电极的第一部分和第二部分彼此隔离，所以在等离子体蚀刻期间仅仅第一多晶硅部分上的电荷有助于栅极绝缘区域的劣化。 在多晶硅栅电极形成之后，第一和第二部分可以通过链路电连接。 从而增加场效应晶体管的性能和/或可靠性。