公开(公告)号：US11974062B2

公开(公告)日：2024-04-30

申请号：US17690829

申请日：2022-03-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Brijesh Jadav ,  Gang Hua ,  Niraj Nandan ,  Rajasekhar Reddy Allu ,  Ankur Ankur ,  Mayank Mangla

IPC: H04N5/262 ,  G06T3/40 ,  G06T7/12 ,  G06T7/60 ,  G06T11/00

CPC classification number: H04N5/2628 ,  G06T3/40 ,  G06T7/12 ,  G06T7/60 ,  G06T11/00

Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.

公开(公告)号：US12111780B2

公开(公告)日：2024-10-08

申请号：US17677638

申请日：2022-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Ankur Ankur ,  Vivek Vilas Dhande ,  Kedar Satish Chitnis ,  Niraj Nandan ,  Brijesh Jadav ,  Shyam Jagannathan ,  Prithvi Shankar Yeyyadi Anantha ,  Santhanakrishnan Narayanan Narayanan

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F13/28 ,  G06F9/4881 ,  G06F13/1673 ,  G06F13/4221 ,  G06F15/7807

Abstract: A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.

公开(公告)号：US20210326229A1

公开(公告)日：2021-10-21

申请号：US17135481

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Rajat Sagar ,  Niraj Nandan ,  Kedar Chitnis ,  Brijesh Jadav ,  Mihir Mody

IPC: G06F11/30 ,  G06F11/07 ,  G06F15/78

Abstract: Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.

公开(公告)号：US20210311782A1

公开(公告)日：2021-10-07

申请号：US17349310

申请日：2021-06-16

Applicant: Texas Instruments Incorporated

Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Jesse Gregory Villarreal, JR. ,  Lucas Carl Weaver ,  Brijesh Jadav ,  Niraj Nandan

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/50

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

公开(公告)号：US11068308B2

公开(公告)日：2021-07-20

申请号：US16298709

申请日：2019-03-11

Applicant: Texas Instruments Incorporated

Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Jesse Gregory Villarreal, Jr. ,  Lucas Carl Weaver ,  Brijesh Jadav ,  Niraj Nandan

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/50

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

公开(公告)号：US20250094221A1

公开(公告)日：2025-03-20

申请号：US18970449

申请日：2024-12-05

Applicant: Texas Instruments Incorporated

Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Jesse Gregory Villarreal, JR. ,  Lucas Carl Weaver ,  Brijesh Jadav ,  Niraj Nandan

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/54

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

公开(公告)号：US12164956B2

公开(公告)日：2024-12-10

申请号：US17349310

申请日：2021-06-16

Applicant: Texas Instruments Incorporated

Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Jesse Gregory Villarreal, Jr. ,  Lucas Carl Weaver ,  Brijesh Jadav ,  Niraj Nandan

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/54

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

公开(公告)号：US11681598B2

公开(公告)日：2023-06-20

申请号：US17135481

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Rajat Sagar ,  Niraj Nandan ,  Kedar Chitnis ,  Brijesh Jadav ,  Mihir Mody

IPC: G06F11/00 ,  G06F11/30 ,  G06F15/78 ,  G06F11/07

CPC classification number: G06F11/3027 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/3072 ,  G06F15/7807

Abstract: Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.

公开(公告)号：US11276134B2

公开(公告)日：2022-03-15

申请号：US16847864

申请日：2020-04-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Rajat Sagar ,  Shashank Dabral ,  Anthony Lell ,  Brijesh Jadav

IPC: G06T5/40 ,  G06T1/20 ,  G06T1/60 ,  G06T5/00

Abstract: A reconfigurable image processing pipeline includes an image signal processor (ISP), a control processor, and a local memory. ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface. For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface. Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.

公开(公告)号：US20190286483A1

公开(公告)日：2019-09-19

申请号：US16298709

申请日：2019-03-11

Applicant: Texas Instruments Incorporated

Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Jesse Gregory Villarreal, JR. ,  Lucas Carl Weaver ,  Brijesh Jadav ,  Niraj Nandan

IPC: G06F9/48 ,  G06F9/54

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.