公开(公告)号：US20250028551A1

公开(公告)日：2025-01-23

申请号：US18908970

申请日：2024-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Naveen BHORIA ,  David Matthew THOMPSON ,  Neelima MURALIDHARAN

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/48 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/121 ,  G06F13/16

Abstract: A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions. The method further includes, in response to an indication that the pipeline does not contain any pending blocking transactions, preventing new snoop transactions from entering the pipeline while permitting new response transactions and victim transactions to enter the pipeline; in response to an indication that the pipeline does not contain any pending snoop transactions, preventing, all new transactions from entering the pipeline; and, in response to an indication that the pipeline does not contain any pending transactions, performing the global operation on the L2 cache.

公开(公告)号：US20240311235A1

公开(公告)日：2024-09-19

申请号：US18673628

申请日：2024-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David Matthew THOMPSON ,  Abhijeet Ashok CHACHAD

IPC: G06F11/10 ,  G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0879 ,  G06F12/0888 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/16 ,  H03M13/15

CPC classification number: G06F11/106 ,  G06F9/30047 ,  G06F9/30101 ,  G06F9/3867 ,  G06F9/4498 ,  G06F9/467 ,  G06F9/4812 ,  G06F9/52 ,  G06F11/1064 ,  G06F11/1068 ,  G06F12/0811 ,  G06F12/0879 ,  G06F12/0895 ,  G06F13/1668 ,  H03M13/1575 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1032 ,  G06F2212/608

Abstract: An example device includes a first memory that store a first set of data; a second memory that stores a second set of data that includes a stored error correcting code (ECC) value; and a controller coupled to the first memory and to the second memory. The controller operates to receive a transaction directed to the first set of data, and based on the transaction perform the following operations: retrieve the second set of data from the second memory; calculate a current ECC value based on the second set of data as retrieved from the second memory; compare the stored ECC value to the current ECC value to determine whether the second set of data includes an error; determine whether the error is correctable; and determine not to access the first memory to perform the transaction based on a determination that the second set of data includes the non-correctable error.

公开(公告)号：US20240152385A1

公开(公告)日：2024-05-09

申请号：US18411763

申请日：2024-01-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Timothy David ANDERSON ,  David Matthew THOMPSON

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/48 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/16

CPC classification number: G06F9/467 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/3867 ,  G06F9/4498 ,  G06F9/4881 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/1668 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/621

Abstract: An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.

公开(公告)号：US20240004793A1

公开(公告)日：2024-01-04

申请号：US18362005

申请日：2023-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Naveen BHORIA

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F12/0808 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0895 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F2212/1021 ,  G06F12/128 ,  G06F12/0828 ,  G06F12/084 ,  G06F9/30047 ,  G06F9/30079 ,  G06F11/3037 ,  G06F12/0808 ,  G06F13/1668 ,  G06F9/3867 ,  G06F9/467 ,  G06F9/544 ,  G06F9/546 ,  G06F12/0895 ,  G06F12/0831 ,  G06F2212/608 ,  G06F12/0815

Abstract: An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.

公开(公告)号：US20230409376A1

公开(公告)日：2023-12-21

申请号：US18456568

申请日：2023-08-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Naveen BHORIA ,  David Matthew THOMPSON ,  Neelima MURALIDHARAN

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/448 ,  G06F11/30 ,  G06F9/54 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0813 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/16 ,  G06F12/0888 ,  G06F12/0831 ,  G06F12/0855

CPC classification number: G06F9/467 ,  G06F9/4881 ,  G06F9/4498 ,  G06F11/3037 ,  G06F9/544 ,  G06F12/0811 ,  G06F9/3867 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0828 ,  G06F9/30098 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/12 ,  G06F9/30047 ,  G06F9/30101 ,  G06F9/30189 ,  G06F13/1668 ,  G06F9/30079 ,  G06F12/0888 ,  G06F12/0831 ,  G06F12/0855 ,  G06F2212/621 ,  G06F2212/1044 ,  G06F2212/1016 ,  G06F12/0804

Abstract: A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions. The method further includes, in response to an indication that the pipeline does not contain any pending blocking transactions, preventing new snoop transactions from entering the pipeline while permitting new response transactions and victim transactions to enter the pipeline; in response to an indication that the pipeline does not contain any pending snoop transactions, preventing, all new transactions from entering the pipeline; and, in response to an indication that the pipeline does not contain any pending transactions, performing the global operation on the L2 cache.

公开(公告)号：US20220237122A1

公开(公告)日：2022-07-28

申请号：US17723559

申请日：2022-04-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Naveen BHORIA ,  Peter Michael HIPPLEHEUSER

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F12/0808 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0895 ,  G06F12/0831

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.

公开(公告)号：US20220229690A1

公开(公告)日：2022-07-21

申请号：US17713287

申请日：2022-04-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Naveen BHORIA ,  David Matthew THOMPSON ,  Neelima MURALIDHARAN

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/448 ,  G06F11/30 ,  G06F9/54 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0813 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/16 ,  G06F12/0888 ,  G06F12/0831 ,  G06F12/0855

Abstract: A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions. The method further includes, in response to an indication that the pipeline does not contain any pending blocking transactions, preventing new snoop transactions from entering the pipeline while permitting new response transactions and victim transactions to enter the pipeline; in response to an indication that the pipeline does not contain any pending snoop transactions, preventing, all new transactions from entering the pipeline; and, in response to an indication that the pipeline does not contain any pending transactions, performing the global operation on the L2 cache.

公开(公告)号：US20200371862A1

公开(公告)日：2020-11-26

申请号：US16882377

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David Matthew THOMPSON ,  Abhijeet Ashok CHACHAD

IPC: G06F11/10 ,  H03M13/15 ,  G06F9/38 ,  G06F9/30 ,  G06F9/46 ,  G06F9/448 ,  G06F9/48 ,  G06F12/0879

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to execute a sequence of scrubbing transactions on the first memory and execute a functional transaction on the second memory. One of the scrubbing transactions and the functional transaction are executed concurrently.

公开(公告)号：US20210365374A1

公开(公告)日：2021-11-25

申请号：US16882344

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Timothy David ANDERSON ,  Pramod Kumar SWAMI ,  Naveen BHORIA ,  David Matthew THOMPSON ,  Neelima MURALIDHARAN

IPC: G06F12/0811 ,  G06F12/10

Abstract: An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.

公开(公告)号：US20200371935A1

公开(公告)日：2020-11-26

申请号：US16882287

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON

IPC: G06F12/0817 ,  G06F12/0813 ,  G06F12/0811

Abstract: A method includes receiving a first request to allocate a line in an N-way set associative cache and, in response to a cache coherence state of a way indicating that a cache line stored in the way is invalid, allocating the way for the first request. The method also includes, in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid, randomly selecting one of the ways in the set. The method also includes, in response to a cache coherence state of the selected way indicating that another request is not pending for the selected way, allocating the selected way for the first request.