公开(公告)号：US12243911B2

公开(公告)日：2025-03-04

申请号：US17017642

申请日：2020-09-10

Applicant: Texas Instruments Incorporated

Inventor： Matthew David Romig ,  Enis Tuncer ,  Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L29/06 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: In described examples of an isolation device, an isolation die that has a set of bond pads is mounted on a first lead frame that has a set of leads. A portion of the bond pads are coupled to respective leads. A first mold material encapsulates the isolation device and the first lead frame forming a first package. The first package is mounted on a second lead frame that has a set of leads. A portion of the first lead frame leads is coupled to respective ones of the second lead frame leads. A second mold material encapsulates the first package and the second lead frame.

公开(公告)号：US12183693B2

公开(公告)日：2024-12-31

申请号：US18450291

申请日：2023-08-15

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L49/02

Abstract: An electronic device includes a magnetic assembly with a multilevel lamination or metallization structure having a core layer, dielectric layers and conductive features formed in metal layers on or between the dielectric layers in respective planes of orthogonal first and second directions and stacked along an orthogonal third direction. The conductive features include first and second patterned conductive features forming first and second windings, first and second conductive capacitor plates, and first and second conductive field plates, in which the first conductive capacitor plate is between the first conductive field plate and the core layer along the third direction and the second conductive capacitor plate is between the second conductive field plate and the core layer along the third direction.

公开(公告)号：US12170164B2

公开(公告)日：2024-12-17

申请号：US17546287

申请日：2021-12-09

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01F27/32 ,  H01F27/02 ,  H01F27/28 ,  H01F41/04 ,  H01L23/495 ,  H01L23/522 ,  H01L23/58 ,  H01L25/00 ,  H01L25/18

Abstract: A magnetic assembly includes a multilevel lamination or metallization structure with a core dielectric layer, dielectric stack layers, a high permittivity dielectric layer, and first and second patterned conductive features, the dielectric stack layers having a first relative permittivity, the high permittivity dielectric layer extends between and contacting the first patterned conductive feature and one of the dielectric stack layers or the core dielectric layer, the high permittivity dielectric layer has a second relative permittivity, and the second relative permittivity is at least 1.5 times the first relative permittivity to mitigate dielectric breakdown in isolation products.

公开(公告)号：US20240355700A1

公开(公告)日：2024-10-24

申请号：US18458367

申请日：2023-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Siraj Akhtar ,  Enis Tuncer ,  Hiep Xuan Nguyen

IPC: H01L23/367 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/308 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16059 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2924/182

Abstract: The present disclosure generally relates to die-package interconnect in a semiconductor device assembly to facilitate thermal conduction. In an example, a semiconductor device assembly includes a semiconductor substrate, a metallization structure, a package substrate, a die-package interconnect, and one or more insulation layers. The metallization structure is on the semiconductor substrate and includes a first metal layer. The die-package interconnect is between the metallization structure and a second metal layer of the package substrate. The die-package interconnect overlaps at least part of a transistor on the semiconductor substrate. The insulation layer(s) are on the metallization structure and have a first portion having a first thickness and a second portion having a second thickness. The first portion is outside a footprint of the transistor. The second portion is between the die-package interconnect and the at least part of the transistor. The first thickness being larger than the second thickness.

公开(公告)号：US11728289B2

公开(公告)日：2023-08-15

申请号：US17330621

申请日：2021-05-26

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L49/02

CPC classification number: H01L23/645 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49503 ,  H01L23/49575 ,  H01L23/49589 ,  H01L28/10

Abstract: An electronic device includes a magnetic assembly with a multilevel lamination or metallization structure having a core layer, dielectric layers and conductive features formed in metal layers on or between the dielectric layers in respective planes of orthogonal first and second directions and stacked along an orthogonal third direction. The conductive features include first and second patterned conductive features forming first and second windings, first and second conductive capacitor plates, and first and second conductive field plates, in which the first conductive capacitor plate is between the first conductive field plate and the core layer along the third direction and the second conductive capacitor plate is between the second conductive field plate and the core layer along the third direction.

公开(公告)号：US11621215B1

公开(公告)日：2023-04-04

申请号：US17538841

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: G01R15/20 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  G01R19/00 ,  H01L43/06

Abstract: In a described example, an apparatus includes: a lead frame having a first portion and having a second portion electrically isolated from the first portion, the first portion having a side surface normal to a planar opposite surface, and having a recessed edge that is notched or chamfered and extending between the side surface and a planar device side surface; a spacer dielectric mounted to the planar device side surface and partially covered by the first portion, and extending beyond the first portion; a semiconductor die mounted to the spacer dielectric, the semiconductor die partially covered by the spacer dielectric and extending beyond the spacer dielectric; the second portion of the lead frame comprising leads coupled to the semiconductor die by electrical connections; and mold compound covering the semiconductor die, the electrical connections, the spacer dielectric, and partially covering the first portion and the second portion.

公开(公告)号：US20220091067A1

公开(公告)日：2022-03-24

申请号：US17027592

申请日：2020-09-21

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: G01N27/70 ,  G01K7/00

Abstract: In a described example, an apparatus includes: at least one electrode having a base on a first surface of a substrate and extending away from the base to an end; a counter-electrode spaced from the end of the at least one electrode, having a first conductive surface facing the end; and a package having a cavity containing the at least one electrode, the substrate, and the counter-electrode, the package having at least one opening configured to allow an atmosphere to enter the cavity.

公开(公告)号：US11201065B2

公开(公告)日：2021-12-14

申请号：US16791152

申请日：2020-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Enis Tuncer ,  Byron Harry Gibbs

IPC: H01L21/56 ,  H01L21/687

Abstract: A method of manufacturing a semiconductor package includes covering a semiconductor die and a plurality of conductive terminals coupled to the semiconductor die in a mold compound, positioning the mold compound between a first pair of electrodes and a second pair of electrodes, and moving a movable electrode of the first pair and a movable electrode of the second pair into a first clamping position. In the first clamping position, each of the first pair of electrodes and the second pair of electrodes electrically couples to a unique subset of the plurality of conductive terminals. The method also includes applying, by the first pair of electrodes, a first voltage to the semiconductor die within the mold compound; and applying, by the second pair of electrodes, a second voltage to the semiconductor die within the mold compound. The second voltage is less than the first voltage.

公开(公告)号：US10770378B1

公开(公告)日：2020-09-08

申请号：US16401828

申请日：2019-05-02

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/495

Abstract: A microelectronic device includes a first conductor and a second conductor, separated by a lateral spacing. The first conductor has a low field contour facing the second conductor. The low field contour has offsets from a tangent line to the first conductor on the low field contour. Each of the offsets increases a separation of the high voltage conductor from the low voltage conductor. A first offset, located from an end of the high voltage conductor, at a first lateral distance of 25 percent of the minimum separation, is 19 percent to 28 percent of the minimum separation. A second offset, located at a second lateral distance of 50 percent of the minimum separation, is 9 percent to 14 percent of the minimum separation. A third offset, located at a third lateral distance of 75 percent of the minimum separation, is 4 percent to 6 percent of the minimum separation.

公开(公告)号：US20190214964A1

公开(公告)日：2019-07-11

申请号：US16356890

申请日：2019-03-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Enis Tuncer ,  Abram Castro

IPC: H03H9/10

CPC classification number: H03H9/1042 ,  H03H9/1007

Abstract: An assembly including an electrical connection substrate formed of material having a Young's modulus of less than about 10 MPa, an acoustic device die having opposite end portions mounted on and electrically connected to the electrical connection substrate and a mold compound layer encapsulating the acoustic device die and interfacing with the substrate.