公开(公告)号：US10186431B2

公开(公告)日：2019-01-22

申请号：US15899203

申请日：2018-02-19

申请人： Texas Instruments Incorporated

发明人： Hiep Xuan Nguyen

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L23/495

摘要： An integrated circuit (“IC”) package mold includes an upper mold platen that defines an upper mold cavity for receiving an upper substrate having a die attach side with a plurality of dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the upper substrate faces upwardly. A lower mold platen defines a lower mold cavity for receiving a lower substrate having a die attach side with a plurality dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the lower substrate faces downwardly.

公开(公告)号：US20220285293A1

公开(公告)日：2022-09-08

申请号：US17752037

申请日：2022-05-24

申请人： Texas Instruments Incorporated

发明人： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC分类号： H01L23/60 ,  H01L23/495 ,  H01L23/00 ,  H01L33/00 ,  H01L33/62

摘要： A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

公开(公告)号：US20170103904A1

公开(公告)日：2017-04-13

申请号：US14880976

申请日：2015-10-12

申请人： Texas Instruments Incorporated

发明人： Hiep Xuan Nguyen

IPC分类号： H01L21/56 ,  H01L21/78

CPC分类号： H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49537 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/85

摘要： An integrated circuit (“IC”) package mold includes an upper mold platen that defines an upper mold cavity for receiving an upper substrate having a die attach side with a plurality of dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the upper substrate faces upwardly. A lower mold platen defines a lower mold cavity for receiving a lower substrate having a die attach side with a plurality dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the lower substrate faces downwardly.

公开(公告)号：US11362047B2

公开(公告)日：2022-06-14

申请号：US16850620

申请日：2020-04-16

申请人： Texas Instruments Incorporated

发明人： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC分类号： H01L23/60 ,  H01L23/495 ,  H01L23/00 ,  H01L33/00 ,  H01L33/62 ,  H01L21/683

摘要： A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

公开(公告)号：US10573537B2

公开(公告)日：2020-02-25

申请号：US16254059

申请日：2019-01-22

申请人： Texas Instruments Incorporated

发明人： Hiep Xuan Nguyen

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/683

摘要： An integrated circuit (“IC”) package mold includes an upper mold platen that defines an upper mold cavity for receiving an upper substrate having a die attach side with a plurality of dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the upper substrate faces upwardly. A lower mold platen defines a lower mold cavity for receiving a lower substrate having a die attach side with a plurality dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the lower substrate faces downwardly.

公开(公告)号：US20180190509A1

公开(公告)日：2018-07-05

申请号：US15899203

申请日：2018-02-19

申请人： Texas Instruments Incorporated

发明人： Hiep Xuan Nguyen

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/683

CPC分类号： H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49537 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/85

摘要： An integrated circuit (“IC”) package mold includes an upper mold platen that defines an upper mold cavity for receiving an upper substrate having a die attach side with a plurality of dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the upper substrate faces upwardly. A lower mold platen defines a lower mold cavity for receiving a lower substrate having a die attach side with a plurality dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the lower substrate faces downwardly.

公开(公告)号：US20240355700A1

公开(公告)日：2024-10-24

申请号：US18458367

申请日：2023-08-30

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Siraj Akhtar ,  Enis Tuncer ,  Hiep Xuan Nguyen

IPC分类号： H01L23/367 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/00

CPC分类号： H01L23/367 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/308 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16059 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2924/182

摘要： The present disclosure generally relates to die-package interconnect in a semiconductor device assembly to facilitate thermal conduction. In an example, a semiconductor device assembly includes a semiconductor substrate, a metallization structure, a package substrate, a die-package interconnect, and one or more insulation layers. The metallization structure is on the semiconductor substrate and includes a first metal layer. The die-package interconnect is between the metallization structure and a second metal layer of the package substrate. The die-package interconnect overlaps at least part of a transistor on the semiconductor substrate. The insulation layer(s) are on the metallization structure and have a first portion having a first thickness and a second portion having a second thickness. The first portion is outside a footprint of the transistor. The second portion is between the die-package interconnect and the at least part of the transistor. The first thickness being larger than the second thickness.

公开(公告)号：US12021004B2

公开(公告)日：2024-06-25

申请号：US17510684

申请日：2021-10-26

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Hiep Xuan Nguyen ,  Jaimal Mallory Wiliamson ,  Arvin Nono Verdeflor ,  Snehamay Sinha

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/3675 ,  H01L21/4817 ,  H01L21/565 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16237 ,  H01L2224/32245 ,  H01L2924/1616 ,  H01L2924/16251 ,  H01L2924/16724

摘要： An electronic device includes a multilevel package substrate, a die, a lid, and a package structure that encloses the die, a portion of the lid, and a portion of the multilevel package substrate, where the package structure fills a gap between a side of another portion of the lid and a side of the die. A method includes attaching a die to a multilevel package substrate with a first side of the die facing the multilevel package substrate and a second side facing away from the multilevel package substrate; positioning a lid on the multilevel package substrate with a first portion of the lid spaced apart from the second side of the die; and forming a package structure that encloses the die and a portion of the multilevel package substrate and fills a gap between the first portion of the lid and the second side of the die.

公开(公告)号：US11978709B2

公开(公告)日：2024-05-07

申请号：US17752037

申请日：2022-05-24

申请人： Texas Instruments Incorporated

发明人： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC分类号： H01L23/60 ,  H01L23/00 ,  H01L23/495 ,  H01L33/00 ,  H01L33/62 ,  H01L21/683 ,  H01L25/16

CPC分类号： H01L23/60 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/28 ,  H01L24/82 ,  H01L33/005 ,  H01L33/62 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/25 ,  H01L25/167 ,  H01L2933/005 ,  H01L2933/0066

摘要： A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

公开(公告)号：US20220319950A1

公开(公告)日：2022-10-06

申请号：US17510684

申请日：2021-10-26

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Hiep Xuan Nguyen ,  Jaimal Mallory Wiliamson ,  Arvin Nono Verdeflor ,  Snehamay Sinha

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L21/56

摘要： An electronic device includes a multilevel package substrate, a die, a lid, and a package structure that encloses the die, a portion of the lid, and a portion of the multilevel package substrate, where the package structure fills a gap between a side of another portion of the lid and a side of the die. A method includes attaching a die to a multilevel package substrate with a first side of the die facing the multilevel package substrate and a second side facing away from the multilevel package substrate; positioning a lid on the multilevel package substrate with a first portion of the lid spaced apart from the second side of the die; and forming a package structure that encloses the die and a portion of the multilevel package substrate and fills a gap between the first portion of the lid and the second side of the die.