公开(公告)号：US20170053854A1

公开(公告)日：2017-02-23

申请号：US15346822

申请日：2016-11-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Juan Alejandro Herbsommer ,  Yong Lin ,  Rongwei Zhang ,  Abram Castro ,  Matthew David Romig

IPC: H01L23/495 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/4952 ,  H01L21/2885 ,  H01L21/4821 ,  H01L21/4825 ,  H01L21/4867 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49572 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49883 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/0612 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1511 ,  H01L2924/1711 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/0665

Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

Abstract translation: 引线框架表面改性的方法包括提供至少一个预制金属引线框架或封装基板（基板）单元，其包括具有管芯焊盘和围绕管芯焊盘的多个接触区域的母材。 包括在固化步骤上形成固体的固体的材料或去除液体载体的烧结步骤的材料的油墨被加成沉积，其包括至少一个（i）芯片垫的区域 和（ii）在至少第一接触区域（第一接触区域）的一个区域。 油墨被烧结或固化以除去液体载体，使得残留基本上固体的油墨残余物。

公开(公告)号：US20160181183A1

公开(公告)日：2016-06-23

申请号：US14968234

申请日：2015-12-14

Applicant: Texas Instruments Incorporated

Inventor： Rongwei Zhang ,  Abram Castro

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/562 ,  H01L24/03 ,  H01L24/04 ,  H01L24/26 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83055 ,  H01L2224/83075 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83862 ,  H01L2224/92247 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/0635

Abstract: The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device and a semiconductor device formed by such method. The method includes providing a leadframe having a top surface; coating said top surface of said leadframe with first and second silane coating; heating said silane coatings to form a pourous layer having a porosity of at least 10%; applying a die to said pourous layer; securing said die to said pourous layer by a die attaching compound; and after the curing of die attach material and wire bonding, a mold compound is applied through molding.

Abstract translation: 本发明涉及一种用于抑制或防止在芯片附着/模具化合物与半导体器件的芯片焊盘和由这种方法形成的半导体器件的界面处的分层的方法。 该方法包括提供具有顶表面的引线框架; 用第一和第二硅烷涂层涂覆所述引线框架的所述顶表面; 加热所述硅烷涂层以形成孔隙率至少为10％的凹陷层; 将模具应用于所述薄层; 通过模具附着化合物将所述模具固定到所述多孔层; 并且在固着芯片附着材料和引线接合之后，通过成型施加模塑料。

公开(公告)号：US20150111344A1

公开(公告)日：2015-04-23

申请号：US14582349

申请日：2014-12-24

Applicant: Texas Instruments Incorporated

Inventor： Bernardo Gallegos ,  Abram Castro

IPC: H01L21/768 ,  H01L21/56

CPC classification number: H01L21/76838 ,  H01L21/56 ,  H01L21/76801 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/12105 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/9202 ,  H01L2924/15311 ,  H01L2224/13347 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Methods of fabricating integrated circuits are disclosed herein. In one embodiment of a method. A die having a side is provided. A conductive stud is connected to the side of the die, wherein the conductive stud has a first end that is connected to the die and an opposite second end. The die is encapsulated said die except for the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud enters the first side of the first dielectric layer. A conductive layer is affixed to the second side of the first dielectric layer. The second side of the conductive stud is affixed to the conductive layer using a conductive adhesive.

Abstract translation: 本文公开了制造集成电路的方法。 在方法的一个实施例中。 提供具有侧面的模具。 导电柱连接到管芯的侧面，其中导电柱具有连接到管芯的第一端和相对的第二端。 除了侧面之外，模具封装了所述模具。 第一电介质层固定在模具的侧面。 第一电介质层具有第一侧和第二侧。 第一介电层的第一侧固定在模具的侧面。 导电螺柱进入第一介电层的第一侧。 导电层固定到第一介电层的第二侧。 使用导电粘合剂将导电柱的第二面固定到导电层。

公开(公告)号：US09875930B2

公开(公告)日：2018-01-23

申请号：US14582349

申请日：2014-12-24

Applicant: Texas Instruments Incorporated

Inventor： Bernardo Gallegos ,  Abram Castro

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/76838 ,  H01L21/56 ,  H01L21/76801 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/12105 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/9202 ,  H01L2924/15311 ,  H01L2224/13347 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Methods of packaging integrated circuits are disclosed herein. In one embodiment of a method. A die having a side is provided. A conductive stud is connected to the side of the die, wherein the conductive stud has a first end that is connected to the die and an opposite second end. The die is encapsulated except for the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud enters the first side of the first dielectric layer. A conductive layer is affixed to the second side of the first dielectric layer. The second side of the conductive stud is affixed to the conductive layer using a conductive adhesive.

公开(公告)号：US09536781B2

公开(公告)日：2017-01-03

申请号：US14831163

申请日：2015-08-20

Applicant: Texas Instruments Incorporated

Inventor： Bernardo Gallegos ,  Abram Castro

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/76858 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4871 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76885 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/03436 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud.

Abstract translation: 本文公开了制造集成电路的方法。 提供具有侧面的模具。 导电螺柱从基本上垂直于侧面的方向从侧面延伸。 第一电介质层固定在模具的侧面。 第一电介质层具有第一侧和第二侧。 第一介电层的第一侧固定在模具的侧面。 导电柱刺穿第一介电层的第一侧。 第一通孔在导电柱和第二侧之间通过第一电介质层形成。 第一通孔电连接到导电柱。

公开(公告)号：US09214440B1

公开(公告)日：2015-12-15

申请号：US14573071

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Rongwei Zhang ,  Abram Castro

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/562 ,  H01L24/03 ,  H01L24/04 ,  H01L24/26 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83055 ,  H01L2224/83075 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83862 ,  H01L2224/92247 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/0635

Abstract: The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device and a semiconductor device formed by such method. The method includes providing a leadframe having a top surface; coating said top surface of said leadframe with first and second silane coating; heating said silane coatings to form a sol-gel layer having a porosity of at least 10%; applying a die to said sol-gel layer; securing said die to said sol-gel layer by a die attaching compound; and after the curing of die attach material and wire bonding, a mold compound is applied through molding.

Abstract translation: 本发明涉及一种用于抑制或防止在芯片附着/模具化合物与半导体器件的芯片焊盘和由这种方法形成的半导体器件的界面处的分层的方法。 该方法包括：提供具有顶表面的引线框架; 用第一和第二硅烷涂层涂覆所述引线框架的所述顶表面; 加热所述硅烷涂层以形成孔隙率至少为10％的溶胶 - 凝胶层; 将模头应用于所述溶胶 - 凝胶层; 通过模具附着化合物将所述模头固定到所述溶胶 - 凝胶层; 并且在固着芯片附着材料和引线接合之后，通过成型施加模塑料。

公开(公告)号：US12087673B2

公开(公告)日：2024-09-10

申请号：US17983249

申请日：2022-11-08

Applicant: Texas Instruments Incorporated

Inventor： Abram Castro ,  Usman Chaudhry ,  Joe Adam Garcia ,  Mahmud Halim Chowdhury

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/67 ,  H01L23/31 ,  H05K1/18 ,  H05K3/34 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/67138 ,  H01L23/3121 ,  H01L23/49541 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/3494 ,  H01L22/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/3511 ,  H05K2201/10636

Abstract: An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a QFN device when it is attached to a printed wiring board (PWB).

公开(公告)号：US11838004B2

公开(公告)日：2023-12-05

申请号：US16356890

申请日：2019-03-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Enis Tuncer ,  Abram Castro

IPC: H03H9/10

CPC classification number: H03H9/1042 ,  H03H9/1007

Abstract: An assembly including an electrical connection substrate formed of material having a Young's modulus of less than about 10 MPa, an acoustic device die having opposite end portions mounted on and electrically connected to the electrical connection substrate and a mold compound layer encapsulating the acoustic device die and interfacing with the substrate.

公开(公告)号：US20190139883A1

公开(公告)日：2019-05-09

申请号：US15807114

申请日：2017-11-08

Applicant: Texas Instruments Incorporated

Inventor： Saumya Gandhi ,  Matthew David Romig ,  Abram Castro

IPC: H01L23/50 ,  H01L23/522 ,  H01L25/065 ,  H01L49/02 ,  H01G4/005 ,  H01L23/532 ,  H01L23/31

Abstract: A packaged semiconductor system, including: at least one electronic device on a device mounting surface of a substrate having terminals for attaching bond wires; at least one discrete component adjacent to the at least one electronic device, a second electrode of the at least one discrete component parallel to and spaced from a first electrode by a component body; the first electrode a metal foil having a protrusion extending laterally from the body and having a surface facing towards the second electrode; bonding wires interconnecting respective terminals of the at least one electronic device, the first electrode and the second electrode, and bonded to the surface of the second electrode and to the protrusion that extend away from the respective surfaces in a same direction; and packaging compound covering portions of the at least one electronic device, the at least one discrete component, and the bonding wires.

公开(公告)号：US09378984B2

公开(公告)日：2016-06-28

申请号：US14520406

申请日：2014-10-22

Applicant: Texas Instruments Incorporated

Inventor： Rongwei Zhang ,  Abram Castro

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/29 ,  B29C45/14 ,  B29C45/00 ,  H01L23/00

CPC classification number: H01L24/48 ,  B29C45/0001 ,  B29C45/0046 ,  B29C45/14655 ,  B29C45/14836 ,  C08K3/10 ,  C08K3/36 ,  C08K7/14 ,  H01B3/40 ,  H01L21/56 ,  H01L21/565 ,  H01L23/295 ,  H01L23/4952 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/4382 ,  H01L2224/43848 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48221 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/485 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/181 ,  H01L2924/3862 ,  H01L2924/00014 ,  H01L2924/20752 ,  H01L2924/078 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip is attached to a substrate with wires spanning from the chip to the substrate is loaded in a heated cavity of a mold. The wire surfaces are coated with an adsorbed layer of molecules of a heterocyclic compound. A pressure chamber of the mold is loaded with a solid pellet of a packaging material including a polymerizable resin. The chamber is connected to the cavity. The vapor of resin molecules is allowed to spread from the chamber to the assembly inside the cavity during the time interval needed to heat the solid pellet for rendering it semi-liquid and to pressurize it through runners before filling the mold cavity, wherein the resin molecules arriving in the cavity are cross-linked by the adsorbed heterocyclic compound molecules into an electrically insulating at least one monolayer of polymeric structures on the wire surfaces.

Abstract translation: 将芯片连接到基板上，从芯片到基板的导线被装载在模具的加热空腔中。 线表面涂覆有杂环化合物分子的吸附层。 模具的压力室装有包括可聚合树脂的包装材料的固体颗粒。 腔室连接到腔体。 在加热固体颗粒以使其呈半液体并在填充模腔之前通过流道对其进行加压所需的时间间隔期间，允许树脂分子的蒸气从腔室扩散到腔内的组件，其中树脂分子 通过吸附的杂环化合物分子到达空腔中的电绝缘的至少一层聚合物结构在电线表面上。