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    Uniform implant regions in a semiconductor ridge of a FinFET
    3.
    发明授权
    Uniform implant regions in a semiconductor ridge of a FinFET 有权

    公开(公告)号：US11437496B2

    公开(公告)日：2022-09-06

    申请号：US17138647

    申请日：2020-12-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ming-Yeh Chuang

    IPC: H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L29/78

    Abstract: A method for fabricating an integrated circuit is disclosed. The method comprises forming a semiconductor ridge over a semiconductor surface of a substrate and forming an implant screen on a top and sidewalls of the semiconductor ridge. The implant screen is at least two times thicker on the top of the semiconductor ridge relative to the sidewalls of the semiconductor ridge. The method further comprises implanting a dopant into the top and sidewalls of the semiconductor ridge.

    finFET with lateral charge balance at the drain drift region
    4.
    发明授权
    finFET with lateral charge balance at the drain drift region 有权

    公开(公告)号：US11916142B2

    公开(公告)日：2024-02-27

    申请号：US17409078

    申请日：2021-08-23

    Applicant: Texas Instruments Incorporated

    Inventor： Ming-Yeh Chuang

    IPC: H01L29/78 ,  H01L27/088 ,  H01L29/40

    CPC classification number: H01L29/7816 ,  H01L27/0886 ,  H01L29/402 ,  H01L29/7851

    Abstract: A semiconductor device includes an extended drain finFET. The drain drift region of the finFET extends between a drain contact region and a body of the finFET. The drain drift region includes an enhanced portion of the drain drift region between the drain contact region and the body. The drain drift region also includes a first charge balance region and a second charge balance region laterally adjacent to, and on opposite sides of, the enhanced portion of the drain drift region. The enhanced portion of the drain drift region and the drain contact region have a first conductivity type; the body, the first charge balance region, and the second charge balance region have a second, opposite, conductivity type. The drain drift region is wider than the body.

    FinFET with lateral charge balance at the drain drift region
    5.
    发明授权
    FinFET with lateral charge balance at the drain drift region 有权

    公开(公告)号：US11152506B1

    公开(公告)日：2021-10-19

    申请号：US16901798

    申请日：2020-06-15

    Applicant: Texas Instruments Incorporated

    Inventor： Ming-Yeh Chuang

    IPC: H01L29/78 ,  H01L29/08 ,  H01L27/088 ,  H01L29/40

    Abstract: A semiconductor device includes an extended drain finFET. The drain drift region of the finFET extends between a drain contact region and a body of the finFET. The drain drift region includes an enhanced portion of the drain drift region between the drain contact region and the body. The drain drift region also includes a first charge balance region and a second charge balance region laterally adjacent to, and on opposite sides of, the enhanced portion of the drain drift region. The enhanced portion of the drain drift region and the drain contact region have a first conductivity type; the body, the first charge balance region, and the second charge balance region have a second, opposite, conductivity type. The drain drift region is wider than the body.

    DIODES WITH A DOG BONE OR CAP-SHAPED JUNCTION PROFILE TO ENHANCE ESD PERFORMANCE, AND OTHER SUBSTRUCTURES, INTEGRATED CIRCUITS AND PROCESSES OF MANUFACTURE AND TESTING
    6.
    发明申请
    DIODES WITH A DOG BONE OR CAP-SHAPED JUNCTION PROFILE TO ENHANCE ESD PERFORMANCE, AND OTHER SUBSTRUCTURES, INTEGRATED CIRCUITS AND PROCESSES OF MANUFACTURE AND TESTING 审中-公开
    具有DOG骨头或CAP形状连接轮廓的二极管，以增强ESD性能和其他结构，集成电路和制造和测试过程

    公开(公告)号：US20130244411A1

    公开(公告)日：2013-09-19

    申请号：US13886466

    申请日：2013-05-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ming-Yeh Chuang

    IPC: H01L21/22 ,  H01L21/265

    CPC classification number: H01L21/22 ,  H01L21/265 ,  H01L27/0255 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/8611

    Abstract: An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed.

    Abstract translation: 集成电路结构包括具有第一导电类型的半导体掺杂区域（NWell）和覆盖所述掺杂区域（NWell）的一部分的层（PSD），并且具有与第二导电类型相反的第二类型的导电性的掺杂 所述掺杂区域（NWell）的第一导电类型和具有横截面角的所述层（PSD），以及在所述层（PSD）下面形成结的所述掺杂区域（NWell）的掺杂， 在所述层（PSD）的角下方附近稀释的掺杂区域（NWell）。 还公开了其它集成电路，子结构，器件，制造工艺和测试过程。

    BIRD'S BEAK PROFILE OF FIELD OXIDE REGION
    8.
    发明公开
    BIRD'S BEAK PROFILE OF FIELD OXIDE REGION 审中-公开

    公开(公告)号：US20230253495A1

    公开(公告)日：2023-08-10

    申请号：US17665381

    申请日：2022-02-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jingjing Chen ,  Ming-Yeh Chuang ,  Guruvayurappan Mathur ,  James Todd ,  Ronald Chin ,  Thomas Lillibridge

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66

    CPC classification number: H01L29/7825 ,  H01L29/4236 ,  H01L29/41758 ,  H01L29/66515

    Abstract: The present disclosure generally relates to a bird's beak profile of a field oxide region. In an example, a semiconductor device structure includes a semiconductor substrate, a dielectric oxide layer, and a field oxide region. The semiconductor substrate has a top surface. The dielectric oxide layer is over the top surface of the semiconductor substrate. The field oxide region is over the semiconductor substrate. The field oxide region is connected to the dielectric oxide layer through a bird's beak region. A lower surface of the bird's beak region interfaces with the semiconductor substrate. In a cross-section along a direction from the field oxide region to the dielectric oxide layer, the lower surface of the bird's beak region does not have a slope with a magnitude that exceeds 0.57735, where rise of the slope is in a direction normal to the top surface of the semiconductor substrate.

    ISOLATION OF SEMICONDUCTOR DEVICE
    9.
    发明公开
    ISOLATION OF SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230246106A1

    公开(公告)日：2023-08-03

    申请号：US17588930

    申请日：2022-01-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ming-Yeh Chuang

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/761

    CPC classification number: H01L29/7816 ,  H01L29/66681 ,  H01L29/0615 ,  H01L21/761

    Abstract: The present disclosure generally relates to isolation of a semiconductor device formed in a semiconductor substrate. In an example, a semiconductor device includes a drift well, a drain region, a first dopant isolation region, and a second dopant isolation region. The drift well, drain region, first dopant isolation region, and second dopant isolation region are disposed in a semiconductor substrate. The drift well, drain region, and second dopant isolation region are doped with a first dopant conductivity type. The first dopant isolation region is doped with a second dopant conductivity type opposite from the first dopant conductivity type. The drain region is disposed within the drift well. The first dopant isolation region circumscribes the drain region. The first dopant isolation region is an electrically floating node. The second dopant isolation region circumscribes the first dopant isolation region.

    FIELD PLATING AT SOURCE SIDE OF GATE BIAS MOSFETS TO PREVENT VT SHIFT
    10.
    发明公开
    FIELD PLATING AT SOURCE SIDE OF GATE BIAS MOSFETS TO PREVENT VT SHIFT 审中-公开

    公开(公告)号：US20230231020A1

    公开(公告)日：2023-07-20

    申请号：US17577133

    申请日：2022-01-17

    Applicant: Texas Instruments Incorporated

    Inventor： Ming-Yeh Chuang

    IPC: H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/765 ,  H01L29/66

    CPC classification number: H01L29/402 ,  H01L29/7816 ,  H01L29/0649 ,  H01L29/1095 ,  H01L21/765 ,  H01L29/66681

    Abstract: The present disclosure introduces a microelectronic device including a source side field plate in a microelectronic device. The microelectronic device may be configured as a metal oxide semiconductor (MOS) transistor, a laterally diffused metal oxide semiconductor (LDMOS) transistor, a drain extended metal oxide semiconductor (DEMOS) transistor, a bipolar junction transistor, a junction field effect transistor, a CMOS transistor, or a gated bipolar device. The source side field plate extends over the source region by a distance which is more than a quarter of the width of the source region. Transistors may suffer from Vt shifts during gate and drain stress over time. The source side field plate reduces the electric field of the transistor near the gate electrode corner on the source side of the transistor. The gate injection current on the source side and electron trapping in the gate oxide thereby reduced which reduces Vt shifts over time.

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