公开(公告)号：US20180151713A1

公开(公告)日：2018-05-31

申请号：US15864157

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo JOH ,  Naveen TIPIRNENI ,  Chang Soo SUH ,  Sameer PENDHARKAR

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20 ,  H01L29/08 ,  H01L21/265 ,  H01L29/06 ,  H01L21/308 ,  H01L21/266

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US20150221747A1

公开(公告)日：2015-08-06

申请号：US14688639

申请日：2015-04-16

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L29/66 ,  H01L29/201 ,  H01L21/8232 ,  H01L49/02 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7833

Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

Abstract translation: 半导体器件包括具有电耦合到GaN FET的漏极节点并且与降压部件串联耦合的过压钳位部件的GaN FET。 降压组件电耦合到为GaN FET提供截止状态偏置的端子。 当GaN FET的漏极节点处的电压小于GaN FET的击穿电压时，过电压钳位部件导通无效电流，并且当电压上升到高于安全电压限度时，导通显着的电流。 降压部件被配置为提供随着来自过电压钳位部件的电流增加而增加的电压降。 半导体器件被配置为当跨越降压元件的电压降达到阈值时接通GaN FET。

公开(公告)号：US20200287033A1

公开(公告)日：2020-09-10

申请号：US16294687

申请日：2019-03-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo SUH ,  Sameer Prakash PENDHARKAR ,  Naveen TIPIRNENI ,  Jungwoo JOH

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L21/02 ,  H01L21/308 ,  H01L29/417 ,  H01L29/423

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

公开(公告)号：US20150270357A1

公开(公告)日：2015-09-24

申请号：US14731744

申请日：2015-06-05

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI ,  Jungwoo JOH

IPC: H01L29/20 ,  H01L27/085 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L27/085 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.

Abstract translation: 包含GaN FET的半导体器件具有在沟道区域外部的隔离栅极结构，其可操作以阻挡半导体器件的两个区域之间的二维电子气体中的电流。 隔离栅极结构与GaN FET的栅极同时形成，并且具有与栅极相同的结构。

公开(公告)号：US20140339671A1

公开(公告)日：2014-11-20

申请号：US14450784

申请日：2014-08-04

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L29/40 ,  H01L21/311

CPC classification number: H01L29/404 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66871 ,  H01L29/78 ,  H01L29/812

Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.

Abstract translation: 半导体器件在至少三个连续区域上形成有台阶式场板，其中在阶梯式场板下的总电介质厚度与先前区域相比在每个区域中至少为10％以上。 各区域的总电介质厚度均匀。 阶梯式场板形成在至少两个电介质层上，至少两个电介质层至少形成一个电介质层，使得图案化的电介质层的至少一部分在阶梯式场板的一个或多个区域中被去除。

公开(公告)号：US20210280702A1

公开(公告)日：2021-09-09

申请号：US17330012

申请日：2021-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo SUH ,  Sameer Prakash PENDHARKAR ,  Naveen TIPIRNENI ,  Jungwoo JOH

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L21/308 ,  H01L29/417 ,  H01L21/02

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

公开(公告)号：US20160247795A1

公开(公告)日：2016-08-25

申请号：US15144104

申请日：2016-05-02

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7833

Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

公开(公告)号：US20160277021A1

公开(公告)日：2016-09-22

申请号：US15168458

申请日：2016-05-31

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H03K17/687 ,  H01L27/092 ,  H01L29/66 ,  H01L27/088 ,  H01L29/20 ,  H01L29/78

CPC classification number: H03K17/6872 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7833 ,  H02M5/2573 ,  H03F3/193 ,  H03F3/195 ,  H03K17/6871 ,  H03K17/6877 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

公开(公告)号：US20140329370A1

公开(公告)日：2014-11-06

申请号：US13886652

申请日：2013-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen TIPIRNENI ,  Sameer PENDHARKAR ,  Rick L. WISE

IPC: H01L21/02

CPC classification number: H01L21/187 ,  H01L21/76254 ,  H01L21/8258

Abstract: An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device.

Abstract translation: 可以通过在具有第一取向的第一硅衬底上生长III-N半导体材料来形成集成的硅和III-N半导体器件。 具有第二不同取向的第二硅衬底在硅器件膜和载体晶片之间具有释放层。 硅器件膜附着到III-N半导体材料上，而硅器件膜通过释放层连接到载体晶片。 随后从硅器件膜移除载体晶片。 在硅器件膜上和/或上形成第一多个部件。 在暴露区域中的III-N半导体材料中和/或上形成第二组分。 在替代方法中，可以在集成硅和III-N半导体器件中的硅器件膜和III-N半导体材料之间设置电介质中间层。

公开(公告)号：US20140327011A1

公开(公告)日：2014-11-06

申请号：US13886429

申请日：2013-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI ,  Jungwoo JOH

IPC: H01L29/20

CPC classification number: H01L29/2003 ,  H01L27/085 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.

Abstract translation: 包含GaN FET的半导体器件具有在沟道区域外部的隔离栅极结构，其可操作以阻挡半导体器件的两个区域之间的二维电子气体中的电流。 隔离栅极结构与GaN FET的栅极同时形成，并且具有与栅极相同的结构。