公开(公告)号：US20200319296A1

公开(公告)日：2020-10-08

申请号：US16376515

申请日：2019-04-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj GUPTA ,  Karthik RAMASUBRAMANIAN

IPC: G01S7/35

Abstract: A system includes a hardware accelerator configured to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.

公开(公告)号：US20220155368A1

公开(公告)日：2022-05-19

申请号：US17351750

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sujaata RAMALINGAM ,  Karthik SUBBURAJ ,  Pankaj GUPTA ,  Anil Varghese MANI ,  Karthik RAMASUBRAMANIAN ,  Indu PRATHAPAN

IPC: G01R31/317 ,  G01R29/26 ,  G11C19/28 ,  G01S7/40

Abstract: A system includes a shift register to store data samples, where the shift register includes a cell under test (CUT), a left guard cell, a right guard cell, a left window, and a right window. The system includes two sets of comparators to compare incoming data samples with data samples in the left window and the right window to compute ranks of the incoming data samples. The system includes a sorted index array to store a rank of the data samples in the shift register. The system includes a selector to select a Kth smallest index from the sorted index array and its corresponding data sample from the shift register. The system includes a target comparator, where the first comparator input receives a data sample from the CUT and the second comparator input receives a Kth smallest data sample, and the comparator output indicates a CFAR target detection.

公开(公告)号：US20210105021A1

公开(公告)日：2021-04-08

申请号：US17061730

申请日：2020-10-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal TANGUDU ,  Pankaj GUPTA ,  Sreenath Narayanan POTTY ,  Ajai PAULOSE ,  Chandrasekhar SRIRAM ,  Mahesh Ravi VARMA ,  Shabbar Abbasi VEJLANI ,  Neeraj SHRIVASTAVA ,  Himanshu VARSHNEY ,  Divyeshkumar Mahendrabhai PATEL ,  Raju Kharataram CHAUDHARI

IPC: H03M1/36 ,  H03M1/12

Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.

公开(公告)号：US20240345805A1

公开(公告)日：2024-10-17

申请号：US18753107

申请日：2024-06-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj GUPTA ,  Karthik SUBBURAJ ,  Sujaata RAMALINGAM ,  Karthik RAMASUBRAMANIAN ,  Indu PRATHAPAN

IPC: G06F7/49 ,  G06F7/501 ,  G06F17/14

CPC classification number: G06F7/49 ,  G06F7/501 ,  G06F17/142

Abstract: A system includes Radix-22 butterfly stages, each including first and second Radix-22 butterfly circuits, in which the first Radix-22 butterfly circuit of a first Radix-22 butterfly stage includes a data input coupled to a system data input, and one of the first Radix-22 butterfly circuit and the second Radix-22 butterfly circuit of a last Radix-22 butterfly stage includes a data output coupled to a system data output. The system further includes a Radix-3 butterfly circuit including a data input coupled to the system data input and a data output selectively couplable to a data input of one of the first or second Radix-22 butterfly circuits of a second or later Radix-22 butterfly stage based on a particular point transform to be performed by the system. A set of memories are used by either the first Radix-22 butterfly stage or the Radix-3 butterfly circuit, depending on the particular point transform.

公开(公告)号：US20200019374A1

公开(公告)日：2020-01-16

申请号：US16237447

申请日：2018-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu PRATHAPAN ,  Puneet SABBARWAL ,  Pankaj GUPTA

IPC: G06F7/24 ,  G06F5/06

Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

公开(公告)号：US20220156044A1

公开(公告)日：2022-05-19

申请号：US17351699

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj GUPTA ,  Karthik SUBBURAJ ,  Sujaata RAMALINGAM ,  Karthik RAMASUBRAMANIAN ,  Indu PRATHAPAN

IPC: G06F7/49 ,  G06F7/501 ,  G06F9/355 ,  G06F17/14 ,  G06F16/901

Abstract: A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.