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公开(公告)号:US20210326136A1
公开(公告)日:2021-10-21
申请号:US17360646
申请日:2021-06-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Timothy D. ANDERSON , Joseph ZBICIAK , Duc BUI , Mel Alan PHIPPS , Todd T. HAHN
IPC: G06F9/30 , G06F9/38 , G06F11/10 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F11/00 , G06F9/345
Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, beginning execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, annulling the first instruction based on the execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction, and executing the second instruction.
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公开(公告)号:US20200371762A1
公开(公告)日:2020-11-26
申请号:US16983429
申请日:2020-08-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Kai CHIRCA , Timothy D. ANDERSON , Todd T. HAHN , Alan L. DAVIS
Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.
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公开(公告)号:US20240281231A1
公开(公告)日:2024-08-22
申请号:US18648583
申请日:2024-04-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Kai CHIRCA , Timothy D. ANDERSON , Todd T. HAHN , Alan L. DAVIS
CPC classification number: G06F8/433 , G06F5/06 , G06F9/30065
Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.
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公开(公告)号:US20200371800A1
公开(公告)日:2020-11-26
申请号:US16422823
申请日:2019-05-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Kai CHIRCA , Timothy D. ANDERSON , Todd T. HAHN , Alan L. DAVIS
IPC: G06F9/30
Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.
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公开(公告)号:US20190243648A1
公开(公告)日:2019-08-08
申请号:US16384537
申请日:2019-04-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Timothy D. ANDERSON , Joseph ZBICIAK , Duc BUI , Mel Alan PHIPPS , Todd T. HAHN
IPC: G06F9/30 , G06F9/345 , G06F9/38 , G06F11/10 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F11/00
CPC classification number: G06F9/3016 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3822 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/10 , G06F11/1048 , G06F12/0875 , G06F12/0897 , G06F2212/452 , G06F2212/60
Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, beginning execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, annulling the first instruction based on the execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction, and executing the second instruction.
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