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公开(公告)号：US20200136631A1
公开(公告)日：2020-04-30
申请号：US16221323
申请日：2018-12-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srinivas Kumar Reddy NARU , Anand Jerry GEORGE , Shagun DUSAD , Visvesvaraya Appala PENTAKOTA
Abstract: A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.
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公开(公告)号：US20200259501A1
公开(公告)日：2020-08-13
申请号：US16860145
申请日：2020-04-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Visvesvaraya Appala PENTAKOTA , Rishi SOUNDARARAJAN , Shagun DUSAD , Chirag Chandrahas SHETTY
Abstract: An analog-to-digital converter, comprising: a voltage to delay circuit having a voltage input, a threshold voltage input, a first output and a second output, wherein a leading edge of the first output is delayed, by a first delay magnitude, in relationship to a leading edge of the second output; and a first stage including: a first logic gate having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, and an output; and a first stage delay comparator having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, a sign signal output and a first stage delay comparator output, wherein the sign signal output represents whether the voltage input is greater than or less than the threshold voltage input. The analog-to-digital converter further includes a digital block having an input connected to the sign signal output of the delay comparator.
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公开(公告)号：US20250023575A1
公开(公告)日：2025-01-16
申请号：US18524652
申请日：2023-11-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rishi SOUNDARARAJAN , Visvesvaraya Appala PENTAKOTA , Sai Vikas KANDIMALLA , Neeraj SHRIVASTAVA , Eeshan MIGLANI
IPC: H03M1/10
Abstract: An analog-to-digital converter (ADC) includes: a time-domain ADC core; and a calibration circuit. The time-domain ADC core includes: a first delay-to-digital stage having a terminal; a second delay-to-digital stage having a terminal; a third delay-to-digital stage having a terminal. The calibration circuitry is coupled to the terminal of the first delay-to-digital stage, the terminal of the second delay-to-digital stage, and the terminal of the third delay-to-digital stage of stages. The calibration circuitry is configured to calibrate the first delay-to-digital stage, the second delay-to-digital stage, and the third delay-to-digital stage based on a zero-crossing calibration and an over-range calibration. The over-range calibration sets a maximum threshold and a minimum threshold for the time-domain ADC relative to a reference voltage.
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公开(公告)号：US20200259502A1
公开(公告)日：2020-08-13
申请号：US16860334
申请日：2020-04-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: An RF receiver including: an antenna cable of receiving an RF signal; a low noise amplifier coupled to the antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, VIN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal. The conversion and folding circuit having: a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals; and
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公开(公告)号：US20220271764A1
公开(公告)日：2022-08-25
申请号：US17182339
申请日：2021-02-23
Applicant: Texas Instruments Incorporated
Inventor： Prasanth K , Eeshan MIGLANI , Visvesvaraya Appala PENTAKOTA , Kartik GOEL , Jagannathan VENKATARAMAN , Sai Aditya Krishnaswamy NURANI
Abstract: A voltage-to-delay converter converts input signals into delay signals, and includes: a first stage for receiving the input signals and for generating intermediate output signals, wherein timing of the intermediate output signals corresponds to voltages of the input signals, and wherein the first stage has a voltage source for providing a rail-to-rail voltage; and a second stage for receiving the intermediate output signals and for generating rail-to-rail output signals, wherein timing of the rail-to-rail output signals corresponds to the timing of the intermediate output signals, and wherein voltage of the rail-to-rail output signals corresponds to the rail-to-rail voltage. A voltage-to-delay converter block is also described. A circuit for receiving differential input signals, generating corresponding output signals, and removing common mode signals from the output signals is also described.
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Patent Agency Ranking
公开(公告)号：US20220200620A1
公开(公告)日：2022-06-23
申请号：US17129180
申请日：2020-12-21
Applicant: Texas Instruments Incorporated
Abstract: A system for converting a voltage into output codes includes logic gates for processing delay signals based on earlier and later arriving signals generated by preamplifiers, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits of the codes, and an auxiliary delay comparator for generating an auxiliary digital signal for use in generating the output codes. A system may include logic gates for generating delay signals based on earlier and later arriving signals, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits, and a multiplexer system for transmitting a selected one of the residue signals.
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公开(公告)号：US20210328595A1
公开(公告)日：2021-10-21
申请号：US16850597
申请日：2020-04-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sai Aditya Krishnaswamy NURANI , Joseph Palackal MATHEW , Prasanth K , Visvesvaraya Appala PENTAKOTA , Shagun DUSAD
Abstract: A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.
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公开(公告)号：US20190379391A1
公开(公告)日：2019-12-12
申请号：US16434526
申请日：2019-06-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Eeshan MIGLANI , Visvesvaraya Appala PENTAKOTA
Abstract: A modulator of an analog to digital converter includes a quantizer component configured to generate a digital signal based on a clock input operating at a sample rate. The modulator further includes a first digital to analog converter (DAC) configured to generate first DAC output at half the sample rate. The modulator further includes a second DAC configured to generate second DAC output at half the sample rate, where the first DAC and the second DAC are updated at alternate cycles of the clock input.
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公开(公告)号：US20250007528A1
公开(公告)日：2025-01-02
申请号：US18394031
申请日：2023-12-22
Applicant: Texas Instruments Incorporated
Inventor： Sovan GHOSH , Visvesvaraya Appala PENTAKOTA
IPC: H03M1/06
Abstract: A circuit includes an amplifier, a pre-driver circuit, and an output circuit. The amplifier has a first input, a second input, and an output. The pre-driver circuit has an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier. The output circuit includes a first transistor and a second transistor. The first transistor has a control terminal coupled to the first output of the pre-driver circuit; a first terminal, and a second terminal coupled to the third output of the pre-driver circuit. The second transistor has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference terminal.
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公开(公告)号：US20220131551A1
公开(公告)日：2022-04-28
申请号：US17570658
申请日：2022-01-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sai Aditya Krishnaswamy NURANI , Joseph Palackal MATHEW , Prasanth K. , Visvesvaraya Appala PENTAKOTA , Shagun DUSAD
Abstract: An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.
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