公开(公告)号：US10446563B1

公开(公告)日：2019-10-15

申请号：US15945552

申请日：2018-04-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiang-Zheng Bo ,  John H. Macpeak ,  Douglas T. Grider

IPC: H01L21/00 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/06 ,  H01L29/49 ,  H01L29/10 ,  H01L21/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L27/02 ,  H01L21/265 ,  G01N21/95 ,  G03F7/20

Abstract: In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.

公开(公告)号：US09177802B2

公开(公告)日：2015-11-03

申请号：US14142251

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Xiang-Zheng Bo ,  Alwin Tsao ,  Douglas T. Grider

IPC: H01L21/336 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/6659

Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

Abstract translation: 包含模拟MOS晶体管的集成电路可以通过以正好四个子植入物注入漏极延伸来形成，其中至少一个子注入在模拟MOS晶体管的源极/漏极栅极边缘处将集成电路的衬底中的掺杂物注入 对于模拟MOS晶体管的每个源极/漏极栅极边缘，相对于模拟MOS晶体管的源极/漏极栅极边缘具有5度至40度的幅度的扭曲角，其中零扭转角子植入物是垂直的 到源极/漏极栅极边缘。 在模拟MOS晶体管的任何源/漏极边缘处，不超过两个子植入物将掺杂剂放置在衬底中。 所有四个子植入物以相同的倾斜角度执行。 在模拟MOS晶体管上不进行光晕注入。

公开(公告)号：US10902921B2

公开(公告)日：2021-01-26

申请号：US16230778

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiang-Zheng Bo ,  Vijaya Subramaniam Vemuri ,  Corey Rollin O'Brien

IPC: G11C11/34 ,  G11C16/16 ,  H01L27/11517 ,  G11C16/04 ,  G11C16/30

Abstract: In some examples, a flash memory comprises a first gate and a second gate located over a semiconductor substrate a third gate located between the first gate and the second gate a floating gate located between the third gate and the semiconductor substrate; and a doped region located within the semiconductor substrate and proximate the second gate, wherein the doped region is configured to receive a positive bias voltage with respect to the semiconductor substrate during an erase cycle.

公开(公告)号：US10811534B2

公开(公告)日：2020-10-20

申请号：US15871785

申请日：2018-01-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiang-Zheng Bo ,  Michelle N. Nguyen ,  Douglas T. Grider

IPC: H01L29/04 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L29/10

Abstract: In some examples, a transistor includes a first well doped with a first-type dopant having a first concentration. The transistor also includes a gate oxide layer on a portion of the first well and a gate layer on the gate oxide layer. The transistor further includes a first segment of a second well doped with the first-type dopant having a second concentration, the first segment underlapping a first portion of the gate layer. The transistor also includes a source region doped with a second-type dopant having a third concentration, the source region in the first segment. The transistor further includes a drain region doped with the second-type dopant having a concentration that is substantially the same as the third concentration.

公开(公告)号：US09245755B2

公开(公告)日：2016-01-26

申请号：US14575552

申请日：2014-12-18

Applicant: Texas Instruments Incorporated

Inventor： Brian E. Hornung ,  Xiang-Zheng Bo ,  Amitava Chatterjee ,  Alwin J. Tsao

IPC: H01L27/07 ,  H01L21/265 ,  H01L29/732 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/1004 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66272 ,  H01L29/6659 ,  H01L29/732 ,  H01L29/7833

Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.

公开(公告)号：US11152068B2

公开(公告)日：2021-10-19

申请号：US16823414

申请日：2020-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiang-Zheng Bo ,  Patrick R. Smith ,  Douglas T. Grider

IPC: H01L29/78 ,  G11C16/04 ,  H01L27/1156 ,  H01L27/108 ,  H01L27/118

Abstract: In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.

公开(公告)号：US09431248B2

公开(公告)日：2016-08-30

申请号：US14874234

申请日：2015-10-02

Applicant: Texas Instruments Incorporated

Inventor： Xiang-Zheng Bo ,  Alwin Tsao ,  Douglas T. Grider

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/6659

Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

公开(公告)号：US09397164B2

公开(公告)日：2016-07-19

申请号：US14944481

申请日：2015-11-18

Applicant: Texas Instruments Incorporated

Inventor： Brian E. Hornung ,  Xiang-Zheng Bo ,  Amitava Chatterjee ,  Alwin J. Tsao

IPC: H01L29/10 ,  H01L27/06

CPC classification number: H01L29/1004 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66272 ,  H01L29/6659 ,  H01L29/732 ,  H01L29/7833

Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.

Abstract translation: 一种集成电路和方法，其具有具有第一基极调谐扩散的深集电极垂直双极晶体管。 MOS晶体管具有第二基极调谐扩散。 第一基调谐扩散和第二基调谐扩散使用相同的植入物形成。

公开(公告)号：US11189626B2

公开(公告)日：2021-11-30

申请号：US16570036

申请日：2019-09-13

Applicant: Texas Instruments Incorporated

Inventor： Xiang-Zheng Bo ,  John H. MacPeak ,  Douglas T. Grider

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/06 ,  H01L29/49 ,  H01L29/10 ,  H01L21/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L29/66 ,  H01L29/423 ,  H01L27/02 ,  H01L21/28 ,  H01L21/265 ,  G01N21/95 ,  G03F7/20

Abstract: In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.

公开(公告)号：US20160079364A1

公开(公告)日：2016-03-17

申请号：US14944481

申请日：2015-11-18

Applicant: Texas Instruments Incorporated

Inventor： Brian E. Hornung ,  Xiang-Zheng Bo ,  Amitava Chatterjee ,  Alwin J. Tsao

IPC: H01L29/10 ,  H01L27/06

CPC classification number: H01L29/1004 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66272 ,  H01L29/6659 ,  H01L29/732 ,  H01L29/7833

Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.