公开(公告)号：US10090351B2

公开(公告)日：2018-10-02

申请号：US15588149

申请日：2017-05-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hiroaki Ashidate ,  Kazumasa Tanida

IPC: H01L27/14 ,  H01L27/146 ,  H01L23/00

Abstract: A semiconductor device according to an embodiment includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a semiconductor oxide film. The pair of substrates is provided with the low-adhesion film interposed therebetween. The metal electrode passes through the low-adhesion film and connects the pair of substrates, and includes, between the pair of substrates, a part thinner than parts embedded in the pair of substrates. A portion of the metal electrode embedded in one substrate is provided with a gap interposed between the portion and the low-adhesion film on the other substrate.

公开(公告)号：US09761463B2

公开(公告)日：2017-09-12

申请号：US14718435

申请日：2015-05-21

Applicant: Toshiba Memory Corporation

Inventor： Kazumasa Tanida ,  Takamitsu Yoshida ,  Kuniaki Utsumi ,  Atsuko Kawasaki

IPC: H01L21/768 ,  H01L21/283 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L27/146

CPC classification number: H01L21/4853 ,  H01L21/76885 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14643 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/03831 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/08059 ,  H01L2224/08111 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80365 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00 ,  H01L2924/00014

Abstract: According to embodiments, a semiconductor device is provided. The semiconductor device includes an insulation layer, an electrode, and a groove. The insulation layer is provided on a surface of a substrate. The electrode is buried in the insulation layer, and a first end surface of the electrode is exposed from the insulation layer. The groove is formed around the electrode on the surface of the substrate. The groove has an outside surface of the electrode as one side surface, and the groove is opened on the surface side of the insulation layer. The first end surface of the electrode buried in the insulation layer protrudes from the surface of the insulation layer.

公开(公告)号：US09935232B2

公开(公告)日：2018-04-03

申请号：US14932470

申请日：2015-11-04

Applicant: Toshiba Memory Corporation

Inventor： Gen Toyota ,  Shouta Inoue ,  Susumu Yamamoto ,  Takamasa Tanaka ,  Takamitsu Yoshida ,  Kazumasa Tanida

IPC: H01L31/18 ,  H01L21/304 ,  H01L21/683

CPC classification number: H01L31/18 ,  H01L21/304 ,  H01L21/6835 ,  H01L27/1464 ,  H01L27/14687 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes a step of grinding to thin a first semiconductor wafer on which a semiconductor device is formed in a state in which a surface of a second semiconductor wafer is fixed on a chuck table of a grinding device after bonding the first semiconductor wafer to the second semiconductor wafer. The method includes a step of fixing a surface of the first semiconductor wafer on the chuck table and grinding the surface of the second semiconductor wafer in a state in which the first semiconductor wafer is bonded to the second semiconductor wafer prior to the grinding step to thin the first semiconductor wafer.