公开(公告)号：US5214304A

公开(公告)日：1993-05-25

申请号：US849834

申请日：1992-03-12

申请人： Taiji Ema ,  Kazunari Shirai

发明人： Taiji Ema ,  Kazunari Shirai

IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L23/532 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/92

CPC分类号： H01L27/10808 ,  H01L21/768 ,  H01L23/53271 ,  H01L27/10852 ,  H01L28/40 ,  H01L29/4232 ,  H01L29/43 ,  H01L29/4916 ,  H01L2924/0002

摘要： A semiconductor device comprises:a insulating film having a first part and a second part, the second part being thiner than the first part; and a polycrystalline silicon film having a first part arranged over the first part of the insulating film and a second part arranged over the second part of the insulating film, the second part of the polycrystalline silicon film having a lower concentration of impurities than that of the first part of the polycrystalline silicon film.

摘要翻译： 一种半导体器件包括：具有第一部分和第二部分的绝缘膜，所述第二部分比所述第一部分更薄; 以及多晶硅膜，其具有布置在绝缘膜的第一部分上的第一部分和布置在绝缘膜的第二部分上的第二部分，多晶硅膜的第二部分的杂质浓度低于绝缘膜的第二部分 第一部分多晶硅膜。

公开(公告)号：US08921981B2

公开(公告)日：2014-12-30

申请号：US13618389

申请日：2012-09-14

申请人： Kazutaka Yoshizawa ,  Taiji Ema ,  Takuya Moriki

发明人： Kazutaka Yoshizawa ,  Taiji Ema ,  Takuya Moriki

IPC分类号： H01L23/544 ,  H01L21/78 ,  H01L21/66

摘要： A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

公开(公告)号：US08530308B2

公开(公告)日：2013-09-10

申请号：US12651058

申请日：2009-12-31

申请人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

发明人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L27/11526 ,  H01L21/76237 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/105 ,  H01L27/11546

摘要： An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.

摘要翻译： 一种集成电路器件包括一个形成有闪存器件的存储器单元，用于形成高压晶体管的相反导电类型的第一和第二阱以及用于低压晶体管的相反导电类型的第三和第四阱，其中至少一个 第一阱和第二阱以及第三阱和第四阱中的至少一个具有比存储单元阱更陡的杂质分布分布。

公开(公告)号：US08283729B2

公开(公告)日：2012-10-09

申请号：US13010255

申请日：2011-01-20

申请人： Tomohiko Tsutsumi ,  Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

发明人： Tomohiko Tsutsumi ,  Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

IPC分类号： H01L23/62

CPC分类号： H01L27/0629 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/0266 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

摘要翻译： 半导体器件包括第一MIS晶体管，其包括栅极绝缘膜92，形成在栅极绝缘膜92和源极/漏极区154上的栅电极108，包括比栅极绝缘膜92厚的栅极绝缘膜96的第二MIS晶体管 形成在栅极绝缘膜96上的栅极电极108，源极/漏极区域154以及连接到源极/漏极区域154之一的镇流电阻器120，在具有绝缘膜的镇流电阻器120上形成的自对准硅绝缘膜146 92，比其间的栅极绝缘膜96薄，以及形成在源极/漏极区154上的硅化物膜156。

公开(公告)号：US20100283092A1

公开(公告)日：2010-11-11

申请号：US12839867

申请日：2010-07-20

申请人： Taiji Ema ,  Tohru Anezaki

发明人： Taiji Ema ,  Tohru Anezaki

IPC分类号： H01L27/108

CPC分类号： H01L27/10852 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897

摘要： The semiconductor device includes a first conductor formed over a semiconductor substrate; a first insulator formed over the first conductor; a second insulator formed over the first insulator, the second insulator having an etching characteristic different from an etching characteristic of the first insulator; a second conductor formed on the second insulator, the second conductor being in contact with the second insulator; a third insulator formed over the second conductor, the third insulator having an etching characteristic different from the etching characteristic of the second insulator; a first contact hole formed through the third insulator and the second conductor, the first contact hole reaching the second insulator; a third conductor formed in the first contact hole, wherein a side wall of the third conductor is electrically connected to a side wall of the second conductor; a second contact hole formed through the third insulator and the first insulator, the second contact hole reaching the first conductor; and a fourth conductor formed in the second contact hole, wherein the fourth conductor is electrically connected to the first conductor.

摘要翻译： 半导体器件包括形成在半导体衬底上的第一导体; 形成在所述第一导体上的第一绝缘体; 形成在所述第一绝缘体上的第二绝缘体，所述第二绝缘体具有与所述第一绝缘体的蚀刻特性不同的蚀刻特性; 形成在所述第二绝缘体上的第二导体，所述第二导体与所述第二绝缘体接触; 形成在所述第二导体上的第三绝缘体，所述第三绝缘体具有与所述第二绝缘体的蚀刻特性不同的蚀刻特性; 通过第三绝缘体和第二导体形成的第一接触孔，第一接触孔到达第二绝缘体; 形成在第一接触孔中的第三导体，其中第三导体的侧壁电连接到第二导体的侧壁; 形成为穿过所述第三绝缘体和所述第一绝缘体的第二接触孔，所述第二接触孔到达所述第一导体; 以及形成在所述第二接触孔中的第四导体，其中所述第四导体电连接到所述第一导体。

公开(公告)号：US20100238716A1

公开(公告)日：2010-09-23

申请号：US12792115

申请日：2010-06-02

申请人： Toru Anezaki ,  Tomohiko Tsutsumi ,  Tatsuji Araya ,  Hideyuki Kojima ,  Taiji Ema

发明人： Toru Anezaki ,  Tomohiko Tsutsumi ,  Tatsuji Araya ,  Hideyuki Kojima ,  Taiji Ema

IPC分类号： G11C11/00 ,  G11C11/34

CPC分类号： H01L27/1104 ,  G11C5/063 ,  G11C11/412 ,  H01L27/11 ,  Y10S257/903

摘要： A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.

摘要翻译： 半导体器件包括第一CMOS反相器，第二CMOS反相器，第一传输晶体管和第二传输晶体管，其中第一和第二传输晶体管分别形成在由器件隔离区限定在半导体器件上的第一和第二器件区域中， 为了彼此并联延伸，第一传输晶体管在第一器件区域上的第一位接触区域处与第一位线接触，第二传输晶体管在第二位线处与第二位线接触，第二位线在第二位接触区域处 器件区域，其中第一位接触区域形成在第一器件区域中，使得所述位接触区域的中心朝向第二器件区域偏移，并且其中第二位接触区域形成在第二器件区域中，使得 第二位接触区域的中心朝向第一器件区域偏移。

公开(公告)号：US07671384B2

公开(公告)日：2010-03-02

申请号：US11209881

申请日：2005-08-24

申请人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

发明人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

IPC分类号： H01L23/62

CPC分类号： H01L27/11526 ,  H01L21/76237 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/105 ,  H01L27/11546

摘要： An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.

摘要翻译： 一种集成电路器件包括一个形成有闪存器件的存储器单元，用于形成高压晶体管的相反导电类型的第一和第二阱以及用于低压晶体管的相反导电类型的第三和第四阱，其中至少一个 第一阱和第二阱以及第三阱和第四阱中的至少一个具有比存储单元阱更陡的杂质分布分布。

公开(公告)号：US20090224332A1

公开(公告)日：2009-09-10

申请号：US12320913

申请日：2009-02-09

申请人： Tomohiko Tsutsumi ,  Toru Anezaki ,  Hideyuki Kojima ,  Taiji Ema

发明人： Tomohiko Tsutsumi ,  Toru Anezaki ,  Hideyuki Kojima ,  Taiji Ema

IPC分类号： H01L27/11 ,  H01L21/8239

CPC分类号： H01L27/115 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11526 ,  H01L27/11546

摘要： An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-LV of a logic circuit region. Ion-implantation is further performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-MV of an I/O region.

公开(公告)号：US07539963B2

公开(公告)日：2009-05-26

申请号：US10969240

申请日：2004-10-21

申请人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki ,  Shinichi Nakagawa

发明人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki ,  Shinichi Nakagawa

IPC分类号： G06F9/45 ,  G06F17/50 ,  G06F9/455

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： The semiconductor group comprises a first semiconductor device including a first design macro and a nonvolatile memory, and a second semiconductor device including a second design macro having identity with the first design macro and including no nonvolatile memory. The first design macro includes a first active region and a first device isolation region formed on a first semiconductor substrate. The second design macro includes a second active region and a second device isolation region formed on a second semiconductor substrate. A curvature radius of an upper end of the first active region in a cross section is larger than a curvature radius of an upper end of the second active region in a cross section. A difference in height between a surface of the first active region and a surface of the first device isolation region is larger than a difference in height between a surface of the second active region and a surface of the device isolation region.

摘要翻译： 半导体组包括包括第一设计宏和非易失性存储器的第一半导体器件，以及包括具有与第一设计宏的标识并且不包括非易失性存储器的第二设计宏的第二半导体器件。 第一设计宏包括形成在第一半导体衬底上的第一有源区和第一器件隔离区。 第二设计宏包括形成在第二半导体衬底上的第二有源区和第二器件隔离区。 横截面中第一有源区的上端的曲率半径大于截面中第二有源区的上端的曲率半径。 第一有源区的表面与第一器件隔离区的表面之间的高度差大于第二有源区的表面与器件隔离区的表面之间的高度差。

公开(公告)号：US07445989B2

公开(公告)日：2008-11-04

申请号：US11044458

申请日：2005-01-28

申请人： Taiji Ema ,  Toru Anezaki

发明人： Taiji Ema ,  Toru Anezaki

IPC分类号： H01L21/253

CPC分类号： H01L21/76802 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11803

摘要： A method of manufacturing a semiconductor device that comprises the steps of: removing a second insulating film on a contact region of a first conductor; forming a second conductive film on the second insulating film; removing the second conductive film on the contact region of the first conductor to make the second conductive film into a second conductor; forming an interlayer insulating film (a third insulating film) covering the second conductor; forming a first hole in the interlayer insulating film on the contact region; and forming a conductive plug, which is electrically connected with the contact region, in the first hole.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在第一导体的接触区域上去除第二绝缘膜; 在所述第二绝缘膜上形成第二导电膜; 去除第一导体的接触区域上的第二导电膜以使第二导电膜成为第二导体; 形成覆盖所述第二导体的层间绝缘膜（第三绝缘膜） 在接触区域上的层间绝缘膜中形成第一孔; 以及在所述第一孔中形成与所述接触区域电连接的导电插塞。