公开(公告)号：US11856876B2

公开(公告)日：2023-12-26

申请号：US17332135

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Ying Lee ,  Shao-Ming Yu ,  Cheng-Chun Chang

IPC: H10N70/00 ,  G11C7/18 ,  G11C8/14 ,  H10B63/00

CPC classification number: H10N70/826 ,  G11C7/18 ,  G11C8/14 ,  H10B63/00 ,  H10N70/021 ,  H10N70/068

Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.

公开(公告)号：US20220310914A1

公开(公告)日：2022-09-29

申请号：US17332135

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Ying Lee ,  Shao-Ming Yu ,  Cheng-Chun Chang

IPC: H01L45/00 ,  H01L27/24 ,  G11C8/14 ,  G11C7/18

Abstract: Semiconductor devices and methods of manufacturing are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.

公开(公告)号：US20230389452A1

公开(公告)日：2023-11-30

申请号：US18447232

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Ying Lee ,  Shao-Ming Yu ,  Cheng-Chun Chang

IPC: H10N70/00 ,  G11C7/18 ,  G11C8/14 ,  H10B63/00

CPC classification number: H10N70/826 ,  G11C7/18 ,  H10N70/068 ,  H10B63/00 ,  H10N70/021 ,  G11C8/14

Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.

公开(公告)号：US09768064B1

公开(公告)日：2017-09-19

申请号：US15210037

申请日：2016-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wei Hsu ,  Chi-Jen Liu ,  Cheng-Chun Chang ,  Yi-Sheng Lin ,  Liang-Guang Chen

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/76883 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53266

Abstract: Formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a low topography region and a high low topography region. The method also includes forming a first dielectric layer over the substrate. The method further includes forming a second dielectric layer over the stop layer. In addition, the method includes forming an opening in the first dielectric layer, the stop layer and the second dielectric layer. The method also includes forming a conductive material layer over the second dielectric layer. The conductive material layer fills the opening. The method further includes performing a polishing process over the conductive material layer until a top surface of the stop layer is exposed.

公开(公告)号：US10157781B2

公开(公告)日：2018-12-18

申请号：US15401238

申请日：2017-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wei Hsu ,  Chi-Jen Liu ,  Cheng-Chun Chang ,  Yi-Sheng Lin ,  Pinlei Edmund Chu ,  Liang-Guang Chen

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/66 ,  H01L21/321 ,  H01L21/02

Abstract: Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a conductive material in the trench and over a top surface of the material layer and polishing the conductive material with a slurry to expose the top surface of the material layer and to form a conductive structure in the trench. The method for forming a semiconductor structure further includes forming a material layer over a substrate and forming a trench in the material layer. The method for forming a semiconductor structure further includes removing the slurry with a reducing solution. In addition, the reducing solution includes a reducing agent, and a standard electrode voltage of the conductive material is greater than a standard electrode voltage of the reducing agent.