公开(公告)号：US20240365553A1

公开(公告)日：2024-10-31

申请号：US18763593

申请日：2024-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui ,  Han-Jong Chia ,  Chenchen Jacob Wang

IPC: H10B51/20 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/10 ,  H10B51/30

Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

公开(公告)号：US11854895B2

公开(公告)日：2023-12-26

申请号：US17813777

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Tzu-Ang Chao ,  Chun-Chieh Lu ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10K10/46 ,  H10K71/12 ,  H10K85/20

CPC classification number: H01L21/823412 ,  H01L21/0262 ,  H01L21/02568 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78696 ,  H10K10/464 ,  H10K10/474 ,  H10K10/484 ,  H10K10/486 ,  H10K71/12 ,  H10K85/221

Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

公开(公告)号：US11729986B2

公开(公告)日：2023-08-15

申请号：US17117570

申请日：2020-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

IPC: H10B51/20 ,  H01L21/02 ,  H01L29/24 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L21/02565 ,  H01L29/24 ,  H10B51/30

Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer, a ferroelectric layer and oxygen scavenging layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. The oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.

公开(公告)号：US11515332B2

公开(公告)日：2022-11-29

申请号：US17108218

申请日：2020-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

IPC: H01L21/00 ,  H01L27/11597 ,  H01L29/24 ,  H01L27/1159 ,  H01L21/477 ,  H01L21/425 ,  H01L21/383 ,  H01L21/02

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

公开(公告)号：US11227828B2

公开(公告)日：2022-01-18

申请号：US16571214

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Chun-Chieh Lu ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L49/02

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a capacitor structure, and a conductive contact. The semiconductor substrate has at least one semiconductor fin thereon. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer and a first metal layer disposed on the ferroelectric layer. The capacitor structure is sandwiched between the conductive contact and the gate structure.

公开(公告)号：US20210375930A1

公开(公告)日：2021-12-02

申请号：US17108218

申请日：2020-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

IPC: H01L27/11597 ,  H01L29/24 ,  H01L27/1159 ,  H01L21/02 ,  H01L21/425 ,  H01L21/383 ,  H01L21/477

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

公开(公告)号：US20210375917A1

公开(公告)日：2021-12-02

申请号：US17113296

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L23/522

Abstract: A process of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive strips. The resulting structure includes a two-dimensional array of horizontal conductive strips. Memory cells may be distributed along the length of each strip to provide a 3D array. The conductive strips together with additional conductive structure that may have a vertical or horizontal orientation allow the memory cells to be addressed individually. Forming the conductive layers with carbon-based material facilitate etching the trenches to a high aspect ratio. Accordingly, forming the conductive layers of carbon-based material enables the memory array to have more layers or to have a higher area density.

公开(公告)号：US20210082801A1

公开(公告)日：2021-03-18

申请号：US16571214

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Chun-Chieh Lu ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a capacitor structure, and a conductive contact. The semiconductor substrate has at least one semiconductor fin thereon. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer and a first metal layer disposed on the ferroelectric layer. The capacitor structure is sandwiched between the conductive contact and the gate structure.

公开(公告)号：US10818562B2

公开(公告)日：2020-10-27

申请号：US16020860

申请日：2018-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Shiang Lin ,  Chia-Cheng Ho ,  Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chih-Sheng Chang

IPC: H01L21/76 ,  H01L29/78 ,  H01L21/66 ,  G01R27/26

Abstract: A method for testing a semiconductor structure includes forming a dielectric layer over a test region of a substrate. A cap layer is formed over the dielectric layer. The dielectric layer and the cap layer are annealed. The annealed cap layer is removed. A ferroelectricity of the annealed dielectric layer is in-line tested.

公开(公告)号：US10727230B2

公开(公告)日：2020-07-28

申请号：US16133028

申请日：2018-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chun-Chieh Lu ,  Meng-Hsuan Hsiao ,  Ling-Yen Yeh ,  Carlos H. Diaz ,  Tung-Ying Lee

IPC: H01L27/092 ,  H01L23/532 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L21/768 ,  H01L21/02 ,  H01L23/538 ,  H01L29/423 ,  H01L29/778 ,  H01L29/45 ,  H01L27/12

Abstract: An integrated semiconductor device includes a first semiconductor device, an ILD layer and a second semiconductor device. The first semiconductor device has a first transistor structure. The ILD layer is over the first semiconductor device and has a thickness in a range substantially from 10 nm to 100 nm. The second semiconductor device is over the ILD layer and has a 2D material layer as a channel layer of a second transistor structure thereof.