公开(公告)号：US12107126B2

公开(公告)日：2024-10-01

申请号：US17747947

申请日：2022-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peter Ramvall ,  Matthias Passlack

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/12 ,  H01L29/15 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L29/122 ,  H01L21/02389 ,  H01L29/152 ,  H01L29/2003 ,  H01L29/66666 ,  H01L29/7827

Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.

公开(公告)号：US11355590B2

公开(公告)日：2022-06-07

申请号：US16836710

申请日：2020-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peter Ramvall ,  Matthias Passlack

IPC: H01L29/78 ,  H01L29/12 ,  H01L29/20 ,  H01L21/02 ,  H01L29/66 ,  H01L29/15

Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.

公开(公告)号：US11158807B2

公开(公告)日：2021-10-26

申请号：US16656583

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Chao-Ching Cheng ,  Matthias Passlack ,  Martin Christopher Holland ,  Tse-An Chen ,  Lain-Jong Li

IPC: H01L51/00 ,  H01L51/05

Abstract: A field effect transistor includes a semiconductor substrate, a first pad layer, carbon nanotubes and a gate structure. The first pad layer is disposed over the semiconductor substrate and comprises a 2D material. The carbon nanotubes are disposed over the first insulating pad layer. The gate structure is disposed over the semiconductor substrate and is vertically stacked with the carbon nanotubes. The carbon nanotubes extend from one side to an opposite side of the gate structure.

公开(公告)号：US12154903B2

公开(公告)日：2024-11-26

申请号：US17674284

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Gerben Doornbos ,  Peter Ramvall

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/308 ,  H01L27/092 ,  H01L29/20 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.

公开(公告)号：US11164939B2

公开(公告)日：2021-11-02

申请号：US16020759

申请日：2018-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Peter Ramvall ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/78 ,  H01L29/04 ,  H01L21/02 ,  H01L21/331

Abstract: A device includes a first epitaxial layer, a second epitaxial layer, an interlayer, a gate dielectric layer, and a gate layer. The interlayer is between the first epitaxial layer and the second epitaxial layer. The gate dielectric layer is around the interlayer. The gate layer is around the gate dielectric layer and the interlayer. The interlayer is slanted with respect to a sidewall of the gate layer.

公开(公告)号：US10797148B2

公开(公告)日：2020-10-06

申请号：US16660455

申请日：2019-10-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark Van Dal ,  Matthias Passlack ,  Martin Christopher Holland

IPC: H01L21/762 ,  H01L29/423 ,  H01L29/20 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  B82Y10/00 ,  H01L29/78 ,  H01L21/764 ,  H01L29/786 ,  H01L29/40 ,  H01L29/775

Abstract: In a method of forming a Group III-V semiconductor layer on a Si substrate, a first source gas containing a Group V element is supplied to a surface of the Si substrate while heating the substrate at a first temperature, thereby terminating the Si surface with the Group V element. Then, a second source gas containing a Group III element is supplied to the surface while heating the substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the Si substrate. After the nucleation layer is formed, the supply of the second source gas is stopped and the substrate is annealed at a third temperature while the first source gas being supplied, thereby forming a seed layer. After the annealing, the second source gas is supplied while heating the substrate at a fourth temperature, thereby forming a body III-V layer semiconductor on the seed layer.

公开(公告)号：US20200287032A1

公开(公告)日：2020-09-10

申请号：US15930285

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/775 ,  H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

公开(公告)号：US10727427B2

公开(公告)日：2020-07-28

申请号：US16120158

申请日：2018-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Timothy Vasen ,  Mark van Dal ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L51/05 ,  H01L27/28 ,  H01L51/00

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

公开(公告)号：US10680062B2

公开(公告)日：2020-06-09

申请号：US16383528

申请日：2019-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark Van Dal ,  Gerben Doornbos ,  Matthias Passlack ,  Martin Christopher Holland

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/775 ,  H01L29/20 ,  B82Y10/00 ,  H01L29/10 ,  H01L21/306 ,  H01L29/04

Abstract: A gate-all-around field effect transistor (GAA FET) includes an InAs nano-wire as a channel layer, a gate dielectric layer wrapping the InAs nano-wire, and a gate electrode metal layer formed on the gate dielectric layer. The InAs nano-wire has first to fourth major surfaces three convex-rounded corner surfaces and one concave-rounded corner surface.

公开(公告)号：US10516039B2

公开(公告)日：2019-12-24

申请号：US16007163

申请日：2018-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Peter Ramvall ,  Matthias Passlack ,  Gerben Doornbos

IPC: H01L21/00 ,  H01L29/66 ,  H01L27/092 ,  H01L29/04 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/8252 ,  H01L29/417 ,  H01L21/84 ,  H01L27/088

Abstract: A tunnel field-effect transistor (TFET), comprising a first source/drain layer comprising a first polar sidewall; a second source/drain layer surrounding the first source/drain layer, wherein the second source/drain layer and the first source/drain layer are of opposite conductivity types; and a semiconductor interlayer between the second source/drain layer and first polar sidewall of the first source/drain layer.